公开(公告)号：US08823041B2

公开(公告)日：2014-09-02

申请号：US13567776

申请日：2012-08-06

申请人： Byoung Sung Kim ,  Sang Eun Lim ,  Jae Jin Lee ,  Yeoun Chul Son

发明人： Byoung Sung Kim ,  Sang Eun Lim ,  Jae Jin Lee ,  Yeoun Chul Son

IPC分类号： H01L33/00 ,  H01L33/62 ,  H01L33/48 ,  H01L33/64 ,  F21V29/00 ,  F21Y101/02

CPC分类号： H01L33/62 ,  F21V29/74 ,  F21V29/75 ,  F21Y2115/10 ,  H01L33/486 ,  H01L33/642 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49107 ,  H01L2924/00014

摘要： Exemplary embodiments of the present invention provide a light emitting diode package including a light emitting diode chip, a lead frame having a chip area on which the light emitting diode chip is arranged, and a package body supporting the lead frame. The lead frame includes a first terminal group arranged at a first side of the chip area and a second terminal group arranged at a second side of the chip area. The first terminal group and the second terminal group each include a first terminal connected to the chip area and a second terminal separated from the chip area, and the width of the first terminal is different than the width of the second terminal outside the package body.

摘要翻译： 本发明的示例性实施例提供一种包括发光二极管芯片的发光二极管封装，其上布置有发光二极管芯片的芯片区域的引线框架和支撑引线框架的封装体。 引线框架包括布置在芯片区域的第一侧的第一端子组和布置在芯片区域的第二侧的第二端子组。 第一端子组和第二端子组各自包括连接到芯片区域的第一端子和与芯片区域分离的第二端子，并且第一端子的宽度不同于封装体外部的第二端子的宽度。

公开(公告)号：US08022784B2

公开(公告)日：2011-09-20

申请号：US12433116

申请日：2009-04-30

申请人： Jae Jin Lee ,  Chul Soon Park ,  Dong Yun Jung ,  Ki Chan Eun

发明人： Jae Jin Lee ,  Chul Soon Park ,  Dong Yun Jung ,  Ki Chan Eun

IPC分类号： H01P5/107

CPC分类号： H01P5/107

摘要： A wireless communication module includes a plurality of monolithic millimeter-wave integrated circuits (MMICs) for signal processing attached to the top surface of a multi-layer low temperature co-fired ceramic substrate; a planar transmission line formed on the top surface of the multi-layer substrate for communications between the MMICs; a metal base attached to the bottom surface of the multi-layer substrate and having an opening to which an antenna is attached; a plurality of vias for connecting the metal base and the planar transmission line within the multi-layer substrate to establish a uniform potential on a ground plane of the multi-layer substrate; an embedded waveguide formed in the opening surrounded with the vias within the multi-layer substrate; and a planar transmission line-to-waveguide transition apparatus for the transition of waves between the planar transmission line and the embedded waveguide.

摘要翻译： 无线通信模块包括多个单层毫米波集成电路（MMIC），用于信号处理，附接到多层低温共烧陶瓷衬底的顶表面; 形成在所述多层基板的上表面上用于MMIC之间的通信的平面传输线; 金属基底，附着在多层基板的底面上，并具有安装有天线的开口; 用于连接多层基板内的金属基底和平面传输线的多个通孔，以在多层基底的接地平面上建立均匀的电位; 在所述开口中形成的嵌入式波导，所述开口被所述多层基板内的通孔包围; 以及用于在平面传输线和嵌入式波导之间转换波的平面传输线到波导转换装置。

公开(公告)号：US20110175769A1

公开(公告)日：2011-07-21

申请号：US12910314

申请日：2010-10-22

申请人： Jae Jin Lee ,  Chung Hwan Kim ,  Min Gun Kim

发明人： Jae Jin Lee ,  Chung Hwan Kim ,  Min Gun Kim

IPC分类号： G01S13/00

CPC分类号： G01S7/034 ,  H01Q1/48 ,  H01Q9/30 ,  H01Q13/00

摘要： Microwave sensor includes an oscillator for generating microwave signals, a power divider for dividing the microwave signals, an antenna for transmitting the divided microwave signals to an outside of the microwave sensor and receiving microwave signals reflected from an object, and a mixer for detecting differences between the microwave signals received through the antenna and the signals input from the power divider and outputting Intermediate Frequency (IF) signals. The antenna includes a ground plate, an antenna pin located at a center of the ground plate, and a metallic wall formed along a circumference of the ground plate. Accordingly, the microwave sensor is advantageous in that it has uniform gain characteristics regardless of an azimuth angle by using a single antenna, functioning as both transmitting and receiving antennas, and a circuit for operating the antenna.

摘要翻译： 微波传感器包括用于产生微波信号的振荡器，用于分割微波信号的功率分配器，用于将分离的微波信号传输到微波传感器的外部并接收从对象反射的微波信号的天线，以及用于检测 通过天线接收的微波信号和从功率分配器输入的信号并输出​​中频（IF）信号。 天线包括接地板，位于接地板中心的天线针脚和沿着接地板的圆周形成的金属壁。 因此，微波传感器的优点在于，通过使用用作发射和接收天线两者的单个天线以及用于操作天线的电路，其具有均匀的增益特性，而不管方位角如何。

公开(公告)号：US20110158026A1

公开(公告)日：2011-06-30

申请号：US12835978

申请日：2010-07-14

申请人： Jin Youp CHA ,  Jae Jin Lee

发明人： Jin Youp CHA ,  Jae Jin Lee

IPC分类号： G11C17/16

CPC分类号： G11C17/16 ,  G11C29/785

摘要： A fuse circuit includes a plurality of fuse sets configured to perform fuse programming and generate fuse signals in response to fuse programming signals and a fuse control unit configured to generate the fuse programming signals depending upon a level of a programming voltage.

摘要翻译： 熔丝电路包括配置成执行熔丝编程并响应于熔丝编程信号产生熔丝信号的多个熔丝组，以及配置成根据编程电压的电平产生熔丝编程信号的熔丝控制单元。

公开(公告)号：US20110116550A1

公开(公告)日：2011-05-19

申请号：US12837022

申请日：2010-07-15

申请人： Jae Jin Lee ,  Moo Kyoung Chung ,  Kyung Su Kim ,  Jun Young Lee ,  Seong Mo Park ,  Nak Woong Eum

发明人： Jae Jin Lee ,  Moo Kyoung Chung ,  Kyung Su Kim ,  Jun Young Lee ,  Seong Mo Park ,  Nak Woong Eum

IPC分类号： H04N11/02

CPC分类号： H04N19/436 ,  H04N19/44 ,  H04N19/61

摘要： A video decoding apparatus and method based on a data and function splitting scheme are disclosed. The video decoding apparatus based on a data and function splitting scheme includes a variable length decoding unit performing variable length decoding and parsing on a bit stream to acquire residual data and a decoding parameter, and splitting the residual data and the decoding parameter by row; and N (N is a natural number of 2 or larger) number of clusters splitting dequantization and inverse discrete cosine transform (IDCT), motion vector prediction, intra prediction and motion compensation, video restoration, and deblocking function into M number of functions, acquiring the residual data, the decoding parameter, and macroblock (MB) processing information of an upper cluster by column, and splitting the information acquired by column into M number of functions to process the same.

摘要翻译： 公开了一种基于数据和功能分解方案的视频解码装置和方法。 基于数据和功能分割方案的视频解码装置包括：可变长度解码单元，对比特流执行可变长度解码和解析以获取残差数据和解码参数，并且逐行分割残留数据和解码参数; 并且N（N是2或更大的自然数）将数量分解解量化和逆离散余弦变换（IDCT），运动矢量预测，帧内预测和运动补偿，视频恢复和去块功能的簇数分为M个函数，获取 按照列逐列的残差数据，解码参数和宏块（MB）处理信息，并将通过列获取的信息拆分为M个函数以进行处理。

公开(公告)号：US20090138684A1

公开(公告)日：2009-05-28

申请号：US12181769

申请日：2008-07-29

申请人： Jae Jin Lee ,  Jun Young Lee ,  Moo Kyoung Chung ,  Seong Mo Park ,  Nak Woong Eum

发明人： Jae Jin Lee ,  Jun Young Lee ,  Moo Kyoung Chung ,  Seong Mo Park ,  Nak Woong Eum

IPC分类号： G06F9/30

CPC分类号： H04N19/42 ,  H04N19/44 ,  H04N19/91

摘要： Provided is an H.264 Context Adaptive Variable Length Coding (CAVLC) decoding method based on an Application-Specific Instruction-set Processor (ASIP). The H.264 CAVLC decoding method includes determining a plurality of comparison bit strings on the basis of a table of a decoding coefficient, storing lengths of the comparison bit strings in a first register, storing code values of the comparison bit strings in a second register, comparing an input bit stream with the comparison bit strings based on the lengths and code values of the comparison bit strings, and determining value of the decoding coefficient according to a result of comparison between the input bit stream and the comparison bit strings. The method extracts a decoding coefficient using a register in an ASIP without accessing a memory and prevents a reduction in speed caused by memory access, thereby increasing the decoding speed of an H.264 decoder.

摘要翻译： 提供了一种基于应用特定指令集处理器（ASIP）的H.264上下文自适应可变长度编码（CAVLC）解码方法。 H.264 CAVLC解码方法包括：基于解码系数的表确定多个比较比特串，将比较比特列的长度存储在第一寄存器中，将比较比特列的代码值存储在第二寄存器 根据比较比特串的长度和码值比较输入比特流与比较比特串，并根据输入比特流和比较比特串之间的比较结果确定解码系数的值。 该方法使用ASIP中的寄存器提取解码系数，而不访问存储器，并且防止由存储器访问引起的速度降低，从而提高H.264解码器的解码速度。

公开(公告)号：US07379502B2

公开(公告)日：2008-05-27

申请号：US10039794

申请日：2001-10-19

申请人： Heui Gi Son ,  Bo Hyung Lee ,  Jae Jin Lee ,  Joo Hyun Lee

发明人： Heui Gi Son ,  Bo Hyung Lee ,  Jae Jin Lee ,  Joo Hyun Lee

IPC分类号： H04B14/04

CPC分类号： H03M5/145 ,  G11B20/1426 ,  G11B2020/1461 ,  G11B2020/1465 ,  G11B2020/1469 ,  H03M7/46

摘要： Disclosed is a method of digital data conversion. The method includes binding input digital data into unit blocks constituted by a plurality of bytes, modulation-coding each byte of the input data blocks by using a code conversion table, and allocating a merging bit in block unit for the modulation-coded input data in block unit.

摘要翻译： 公开了一种数字数据转换的方法。 该方法包括将输入数字数据结合成由多个字节构成的单位块，通过使用代码转换表对输入数据块的每个字节进行调制编码，并以块为单位分配用于调制编码的输入数据的合并位 块单位。

公开(公告)号：US06943585B2

公开(公告)日：2005-09-13

申请号：US10694966

申请日：2003-10-28

申请人： Jae Jin Lee ,  Kang Seol Lee

发明人： Jae Jin Lee ,  Kang Seol Lee

IPC分类号： H03K19/018 ,  G11C7/10 ,  H03K19/00 ,  H03K19/0948

CPC分类号： G11C7/1078 ,  G11C7/1084 ,  G11C2207/2227 ,  H03K19/0016

摘要： Disclosed is an input apparatus used in a SSTL interface, which comprises a differential buffer for comparing an external input signal with a reference potential inputted from an external, and a CMOS buffer for buffering the external input signal. In the input apparatus, the CMOS buffer operates when a command signal or an address signal is not inputted from an external, and when a predetermined operation such as a refresh operation is performed, thereby reducing the power consumption in a standby mode. Further, in order to prevent the input apparatus from abnormally operating when the reference potential is not maintained in the normal operation range, a reference potential level detecting circuit is further included in the input apparatus, so that the CMOS buffer operates when the reference potential deviates from a predetermined normal operation range. Furthermore, in order to enable an input buffer to operate as the CMOS when an input signal fully swings, a circuit for detecting a potential of an input signal inputted from an external is further included in the input apparatus.

摘要翻译： 公开了一种在SSTL接口中使用的输入装置，其包括用于将外部输入信号与从外部输入的参考电位进行比较的差分缓冲器和用于缓冲外部输入信号的CMOS缓冲器。 在输入装置中，当没有从外部输入命令信号或地址信号时，并且当执行诸如刷新操作的预定操作时，CMOS缓冲器操作，从而降低待机模式下的功耗。 此外，为了防止输入装置在基准电位不保持在正常工作范围时异常工作，在输入装置中还包括基准电位电平检测电路，使得CMOS缓冲器在参考电位偏移 从预定的正常操作范围。 此外，为了使输入缓冲器在输入信号完全摆动时作为CMOS工作，在输入装置中还包括用于检测从外部输入的输入信号的电位的电路。

公开(公告)号：US06940325B2

公开(公告)日：2005-09-06

申请号：US10672990

申请日：2003-09-26

申请人： Jae Jin Lee

发明人： Jae Jin Lee

IPC分类号： G11C11/407 ,  H03L7/06 ,  H03L7/081

CPC分类号： H03L7/0805 ,  H03L7/0814

摘要： A DLL circuit synchronizes an external input clock applied from an outside of a system with an internal input clock used inside the system using a divider unit. The DLL circuit includes a detection unit for detecting whether a pulse width of the external input clock is narrower than a reference set value. The divider unit outputs a first divided signal when it is detected that the pulse width of the external input clock is wider than the reference set value, and outputs a second divided signal when it is detected that the pulse width of the external input clock is shorter than the reference set value. The DLL circuit can normally operate even when the period of the external input clock is short.

摘要翻译： DLL电路使用分频器单元将从系统外部施加的外部输入时钟与系统内部使用的内部输入时钟同步。 DLL电路包括检测单元，用于检测外部输入时钟的脉冲宽度是否比参考设定值窄。 当检测到外部输入时钟的脉冲宽度大于参考设定值时，除法器单元输出第一分频信号，并且当检测到外部输入时钟的脉冲宽度较短时输出第二分频信号 比参考设定值。 即使当外部输入时钟的周期短时，DLL电路也可以正常工作。

公开(公告)号：US06845050B2

公开(公告)日：2005-01-18

申请号：US10755732

申请日：2004-01-12

申请人： Jae Jin Lee

发明人： Jae Jin Lee

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C7/00 ,  G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/408 ,  G11C11/409 ,  G11C11/00

CPC分类号： G11C7/106 ,  G11C5/14 ,  G11C7/06 ,  G11C7/1051 ,  G11C7/22

摘要： A signal delay control circuit for use in a semiconductor memory device is disclosed. The circuit includes a first reference voltage generating unit for generating a first reference voltage; a second reference voltage generating unit for generating a second reference voltage that is lower than the first reference voltage; a control signal generating unit for generating a clock signal to drive input and output operations of internal circuits; and an impedance circuit in circuit with the first and second reference voltage generating units for generating a plurality of reference voltages to be applied to the internal circuits wherein the reference voltages are set in accordance with a distance between the control signal generating unit and the respective one of the internal circuits.

摘要翻译： 公开了一种用于半导体存储器件的信号延迟控制电路。 该电路包括用于产生第一参考电压的第一参考电压产生单元; 第二参考电压产生单元，用于产生低于第一参考电压的第二参考电压; 控制信号产生单元，用于产生用于驱动内部电路的输入和输出操作的时钟信号; 以及与第一和第二参考电压产生单元电路的电路中的阻抗电路，用于产生要施加到内部电路的多个参考电压，其中参考电压根据控制信号产生单元和相应的一个 的内部电路。