公开(公告)号：US20110273248A1

公开(公告)日：2011-11-10

申请号：US12776444

申请日：2010-05-10

Applicant: Sean Timothy Nicolson ,  Scott Kevin Reynolds

Inventor： Sean Timothy Nicolson ,  Scott Kevin Reynolds

IPC: H01P1/22

CPC classification number: H03H7/25 ,  H01P1/15 ,  H04B1/40

Abstract: An input attenuator may include a first input circuit having an RF_IN+ terminal, a first node, a transmission line, a DC blocking capacitor, a second node, a third node, and an output terminal coupled in series, the first node selectively coupled to ground via a serially coupled capacitor and a first silicon germanium heterojunction bipolar transistor, the second node coupled to ground via a capacitor, and the third node selectively coupled to ground via a DC blocking capacitor, a resistor, and a second silicon germanium heterojunction bipolar transistor coupled in series. The input attenuator may also include a second input circuit parallel to the first input circuit and having structure similar to the first input circuit.

Abstract translation: 输入衰减器可以包括具有RF_IN +端子，第一节点，传输线，隔直流电容器，第二节点，第三节点和串联耦合的输出端的第一输入电路，第一节点选择性地耦合到地 经由串联耦合电容器和第一硅锗异质结双极晶体管，第二节点通过电容器耦合到地，并且第三节点经由隔直流电容器，电阻器和第二硅锗异质结双极晶体管选择性地耦合到地， 系列。 输入衰减器还可以包括与第一输入电路并联并具有与第一输入电路类似的结构的第二输入电路。

公开(公告)号：US07825741B2

公开(公告)日：2010-11-02

申请号：US12127389

申请日：2008-05-27

Applicant: Scott Kevin Reynolds ,  Mehmet Soyuer ,  Chinmaya Mishra

Inventor： Scott Kevin Reynolds ,  Mehmet Soyuer ,  Chinmaya Mishra

IPC: H03K3/03

CPC classification number: H03F3/16 ,  G06F17/5063 ,  H03F3/72 ,  H03G1/0088

Abstract: A method of generating an output signal from an input signal includes a step of generating a set of n signals, n being an integer greater than or equal to 3, by generating a signal for each integer i such that 0≦i≦(n−1), each signal within the set having the same frequency and approximately equal amplitude and a phase equal to (360/n)i degrees. The method also includes a step of inputting each of the set of n signals to a gate terminal of a corresponding one of a set of n transistors. Each of the transistors has a source terminal electrically connected to a common voltage drain and each of the transistors has a drain terminal electrically connected to a coupling. The coupling is electrically connected to a common voltage source. The output signal at the coupling has a frequency equal to the frequency of the input signal multiplied by n.

Abstract translation: 一种从输入信号生成输出信号的方法包括：通过为每个整数i产生一个信号，产生一组n个信号，n为大于或等于3的整数，使得0＆nlE; i＆nlE;（n- 1）中，组内的每个信号具有相同的频率和近似相等的幅度以及等于（360 / n）i度的相位。 该方法还包括将n组信号中的每一个输入到一组n个晶体管中的相应一个的栅极端的步骤。 每个晶体管具有电连接到公共电压漏极的源极端子，并且每个晶体管具有电连接到耦合器的漏极端子。 耦合电连接到公共电压源。 耦合时的输出信号的频率等于输入信号乘以n的频率。

公开(公告)号：US20090102542A1

公开(公告)日：2009-04-23

申请号：US12123735

申请日：2008-05-20

Applicant: Scott Kevin Reynolds

Inventor： Scott Kevin Reynolds

IPC: H03K17/60 ,  H03K17/56 ,  G06F17/50

CPC classification number: H03F3/16 ,  G06F17/5063 ,  H03F3/72 ,  H03G1/0088

Abstract: A circuit includes an amplifier having an input and an output; and at least one transistor comprising at least one terminal and at least one isolated well. The input of the amplifier is electrically connected to the at least one terminal of the transistor; and the output of the amplifier is electrically connected to the at least one isolated well of the at least one transistor.

Abstract translation: 电路包括具有输入和输出的放大器; 以及包括至少一个端子和至少一个隔离阱的至少一个晶体管。 放大器的输入电连接到晶体管的至少一个端子; 并且放大器的输出电连接到至少一个晶体管的至少一个隔离的阱。

公开(公告)号：US07346645B2

公开(公告)日：2008-03-18

申请号：US10981820

申请日：2004-11-05

Applicant: Scott Kevin Reynolds

Inventor： Scott Kevin Reynolds

IPC: G06G7/02

CPC classification number: H04B10/25133 ,  H03H15/02

Abstract: A transverse form analog finite impulse response filter. The filter has an input and an output. A first set of passive delay elements connected in serial to the input, and a second set of passive delay elements are connected in serial to the output. Transconductors are connected in parallel with the first plurality of passive delay elements and the second plurality of passive delay elements. A set of buffer amplifiers is connected to the passive delay elements in the first set of passive delay elements and in the set of passive delay elements. The buffer amplifiers cause a reduction in loss in the passive delay elements.

Abstract translation: 横向模拟有限脉冲响应滤波器。 滤波器具有输入和输出。 串联连接到输入端的第一组被动延迟元件，和第二组被动延迟元件串联连接到输出端。 跨导体与第一多个无源延迟元件和第二多个被动延迟元件并联连接。 一组缓冲放大器连接到第一组被动延迟元件和被动延迟元件组中的被动延迟元件。 缓冲放大器可以减少被动延迟元件的损耗。

公开(公告)号：US06414806B1

公开(公告)日：2002-07-02

申请号：US09677346

申请日：2000-10-02

Applicant: Sudhir Muniswamy Gowda ,  Scott Kevin Reynolds

Inventor： Sudhir Muniswamy Gowda ,  Scott Kevin Reynolds

IPC: G11B502

CPC classification number: G11B5/02 ,  G11B5/012 ,  G11B5/6076 ,  G11B20/10009 ,  G11B2005/0016

Abstract: A method for detecting and compensating for thermal asperity in data signals, including the steps of detecting thermal asperity in the data signals and adjusting a parameter prior to amplification of the data signals.

Abstract translation: 一种用于检测和补偿数据信号中的热不均匀性的方法，包括以下步骤：检测数据信号中的热不均匀性，并在数据信号放大之前调整参数。

公开(公告)号：US06090710A

公开(公告)日：2000-07-18

申请号：US911808

申请日：1997-08-15

Applicant: Panayotis Constantinou Andricacos ,  Hariklia Deligianni ,  James McKell Edwin Harper ,  Chao-Kun Hu ,  Dale Jonathan Pearson ,  Scott Kevin Reynolds ,  King-Ning Tu ,  Cyprian Emeka Uzoh

Inventor： Panayotis Constantinou Andricacos ,  Hariklia Deligianni ,  James McKell Edwin Harper ,  Chao-Kun Hu ,  Dale Jonathan Pearson ,  Scott Kevin Reynolds ,  King-Ning Tu ,  Cyprian Emeka Uzoh

IPC: C22C9/00 ,  C22C9/02 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/532 ,  H01L21/44

CPC classification number: H01L23/49866 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/49822 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10T428/12014 ,  Y10T428/12903 ,  Y10T428/265

Abstract: A method of making Copper alloys containing between 0.01 and 10 weight percent of at least one alloying element selected from carbon, indium and tin is disclosed for improved electromigration resistance, low resistivity and good corrosion resistance that can be used in chip and package interconnections and conductors by first forming the copper alloy and then annealing it to cause the diffusion of the alloying element toward the grain boundaries between the grains in the alloy are disclosed.

Abstract translation: 公开了一种制备含有0.01至10重量％的至少一种选自碳，铟和锡的合金元素的铜合金的方法，用于改善可用于芯片和封装互连和导体的电迁移率，低电阻率和良好的耐腐蚀性 通过首先形成铜合金，然后退火以使合金元素向合金中的晶粒之间的晶界扩散。

公开(公告)号：US6063506A

公开(公告)日：2000-05-16

申请号：US093500

申请日：1998-06-08

Applicant: Panayotis Constantinou Andricacos ,  Hariklia Deligianni ,  James McKell Edwin Harper ,  Chao-Kun Hu ,  Dale Jonathan Pearson ,  Scott Kevin Reynolds ,  King-Ning Tu ,  Cyprian Emeka Uzoh

Inventor： Panayotis Constantinou Andricacos ,  Hariklia Deligianni ,  James McKell Edwin Harper ,  Chao-Kun Hu ,  Dale Jonathan Pearson ,  Scott Kevin Reynolds ,  King-Ning Tu ,  Cyprian Emeka Uzoh

IPC: C22C9/00 ,  C22C9/02 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/532 ,  B32B15/20 ,  H01B5/02 ,  H01L21/44

CPC classification number: H01L23/49866 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/49822 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10T428/12014 ,  Y10T428/12903 ,  Y10T428/265

Abstract: Copper alloys containing between 0.01 and 10 weight percent of at least one alloying element selected from carbon, indium and tin for improved electromigration resistance, low resistivity and good corrosion resistance that can be used in chip and package interconnections and a method of making such interconnections and conductors by first forming the copper alloy and then annealing it to cause the diffusion of the alloying element toward the grain boundaries between the grains in the alloy are disclosed.

Abstract translation: 含有0.01至10重量％的至少一种选自碳，铟和锡的合金元素的铜合金，用于改善电迁移率，低电阻率和良好的耐腐蚀性，可用于芯片和封装互连，以及制造这种互连和 导体，首先形成铜合金，然后退火以使合金元素向合金中的晶粒之间的晶界扩散。

公开(公告)号：US08594609B2

公开(公告)日：2013-11-26

申请号：US13046377

申请日：2011-03-11

Applicant: Alberto Valdes Garcia ,  Chinmaya Mishra ,  Scott Kevin Reynolds

Inventor： Alberto Valdes Garcia ,  Chinmaya Mishra ,  Scott Kevin Reynolds

IPC: H04B1/26 ,  H03D7/14 ,  H04B1/30

CPC classification number: H03D7/1441 ,  H03D7/1475 ,  H03D7/1491 ,  H03D2200/0007 ,  H03D2200/0043 ,  H03D2200/0084 ,  H04B1/30

Abstract: A sub-harmonic mixer includes a first transistor having a source and a drain and a second transistor having a source connected to the source of the first transistor and a drain connected to the drain of the first transistor. A mixing transistor is configured to be biased in a linear operating region. The mixing transistor includes a drain coupled to the sources of the first transistor and the second transistor. The mixing transistor has its drain driven by a signal at twice a local oscillator (LO) frequency and its gate driven by a radio frequency (RF) signal while the mixing transistor is biased in the linear region such that a process of frequency doubling and mixing are performed simultaneously.

Abstract translation: 子谐波混合器包括具有源极和漏极的第一晶体管和具有连接到第一晶体管的源极的源极和连接到第一晶体管的漏极的漏极的第二晶体管。 混合晶体管被配置为在线性工作区域中偏置。 混合晶体管包括耦合到第一晶体管和第二晶体管的源极的漏极。 混合晶体管的漏极由本地振荡器（LO）频率的两倍的信号驱动，其栅极由射频（RF）信号驱动，而混合晶体管被偏置在线性区域中，使得频率倍增和混合的过程 同时进行。

公开(公告)号：US08482364B2

公开(公告)日：2013-07-09

申请号：US12788910

申请日：2010-05-27

Applicant: Brian Allan Floyd ,  Arun Sridhar Natarajan ,  Scott Kevin Reynolds ,  Mehmet Soyuer ,  Alberto Valdes Garcia

Inventor： Brian Allan Floyd ,  Arun Sridhar Natarajan ,  Scott Kevin Reynolds ,  Mehmet Soyuer ,  Alberto Valdes Garcia

IPC: H01P5/12

CPC classification number: H01P5/16

Abstract: A differential cross-coupled power combiner in one aspect comprises a plurality of inputs, an output, a plurality of differential transmission lines each coupled between a corresponding one of the inputs and the output, and at least one set of additional differential transmission lines arranged in series between any two of the inputs. First and second ones of the additional differential transmission lines in the set are coupled to one another using a cross-coupling arrangement. Other aspects of the invention provide a differential cross-coupled power divider, communication system receivers and transmitters incorporating respective power combiners and dividers, and integrated circuit implementations of power combiners and dividers.

Abstract translation: 差分交叉耦合功率组合器在一个方面包括多个输入，输出，多个差分传输线，每个差分传输线分别耦合在相应的一个输入端和输出端之间，以及至少一组附加差分传输线路，其布置在 任何两个输入之间的串联。 组中的第一和第二附加差动传输线使用交叉耦合装置彼此耦合。 本发明的其它方面提供了差分交叉耦合功率分配器，包括各个功率组合器和分频器的通信系统接收器和发射器以及功率组合器和分频器的集成电路实现。

公开(公告)号：US07962114B2

公开(公告)日：2011-06-14

申请号：US11622812

申请日：2007-01-12

Applicant: Alberto Valdes Garcia ,  Chinmaya Mishra ,  Scott Kevin Reynolds

Inventor： Alberto Valdes Garcia ,  Chinmaya Mishra ,  Scott Kevin Reynolds

IPC: H04B1/26

CPC classification number: H03D7/1441 ,  H03D7/1475 ,  H03D7/1491 ,  H03D2200/0007 ,  H03D2200/0043 ,  H03D2200/0084 ,  H04B1/30

Abstract: A sub-harmonic mixer includes a first transistor having a source and a drain and a second transistor having a source connected to the source of the first transistor and a drain connected to the drain of the first transistor. A mixing transistor is configured to be biased in a linear operating region. The mixing transistor includes a drain coupled to the sources of the first transistor and the second transistor. The mixing transistor has its drain driven by a signal at twice a local oscillator (LO) frequency and its gate driven by a radio frequency (RF) signal while the mixing transistor is biased in the linear region such that a process of frequency doubling and mixing are performed simultaneously.

Abstract translation: 子谐波混合器包括具有源极和漏极的第一晶体管和具有连接到第一晶体管的源极的源极和连接到第一晶体管的漏极的漏极的第二晶体管。 混合晶体管被配置为在线性工作区域中偏置。 混合晶体管包括耦合到第一晶体管和第二晶体管的源极的漏极。 混合晶体管的漏极由本地振荡器（LO）频率的两倍的信号驱动，其栅极由射频（RF）信号驱动，而混合晶体管被偏置在线性区域中，使得频率倍增和混合的过程 同时进行。