中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

19 records (took 0.017 seconds)

    Compound electrode stack capacitor
    2.
    发明授权
    Compound electrode stack capacitor 失效
    复合电极堆叠电容器

    公开(公告)号：US5825609A

    公开(公告)日：1998-10-20

    申请号：US636457

    申请日：1996-04-23

    Applicant: Panayotis Constantinou Andricacos ,  David Edward Kotecki ,  Katherine Lynn Saenger

    Inventor： Panayotis Constantinou Andricacos ,  David Edward Kotecki ,  Katherine Lynn Saenger

    IPC: H01L21/8247 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792 ,  H01G4/06

    CPC classification number: H01L28/82 ,  H01L21/76849 ,  H01L21/7687 ,  H01L27/1085 ,  H01L28/91 ,  H01L28/55

    Abstract: This invention is directed to a semiconductor memory device including a storage element having a ferroelectric material or a capacitor dielectric material between a top (plate) electrode and a bottom (stack) electrode. In particular, the invention pertains to the design and fabrication of the stack electrode, which is described as compound because it is comprised of two or more materials which are either patterned separately (with at least one material being deposited and patterned prior to the deposition of the others), or arranged so that each of the component materials significantly contributes to the area over which the ferroelectric or capacitor dielectric is initially deposited. These compound stack electrodes may offer ease in processing, more economical use of noble metal materials, and potentially increased mechanical stability (e.g., resistance to hillocking) relative to solid, single-material electrodes of the same dimensions.

    Abstract translation: 本发明涉及一种半导体存储器件，其包括在顶部（板）电极和底部（堆叠）电极之间具有铁电材料或电容器电介质材料的存储元件。 特别地，本发明涉及堆叠电极的设计和制造，其被描述为化合物，因为它由两种或更多种材料组成，这两种或多种材料是单独图案化的（至少一种材料在沉积之前沉积和图案化 其他），或者被布置成使得每个组分材料显着地有助于初始沉积铁电体或电容器电介质的区域。 相对于相同尺寸的固体单材料电极，这些复合堆叠电极可以提供易于处理，更经济地使用贵金属材料以及潜在的增加的机械稳定性（例如抵抗小丘）。

    Method for forming electromigration-resistant structures by doping
    4.
    发明授权
    Method for forming electromigration-resistant structures by doping 有权
    通过掺杂形成电迁移结构的方法

    公开(公告)号：US06268291B1

    公开(公告)日：2001-07-31

    申请号：US09204185

    申请日：1998-12-03

    Applicant: Panayotis Constantinou Andricacos ,  Cyril Cabral, Jr. ,  Christopher Carr Parks ,  Kenneth Parker Rodbell ,  Roger Yen-Luen Tsai

    Inventor： Panayotis Constantinou Andricacos ,  Cyril Cabral, Jr. ,  Christopher Carr Parks ,  Kenneth Parker Rodbell ,  Roger Yen-Luen Tsai

    IPC: H01L2100

    CPC classification number: H01L21/2885 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76859 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76886 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2224/29099 ,  H01L2924/00

    Abstract: A method for forming a copper conductor in an electronic structure by first depositing a copper composition in a receptacle formed in the electronic structure, and then adding impurities into the copper composition such that its electromigration resistance is improved is disclosed. In the method, the copper composition can be deposited by a variety of techniques such as electroplating, physical vapor deposition and chemical vapor deposition. The impurities which can be implanted include those of C, O, Cl, S and N at a suitable concentration range between about 0.01 ppm by weight and about 1000 ppm by weight. The impurities can be added by three different methods. In the first method, a copper seed layer is first deposited into a receptacle and an ion implantation process is carried out on the seed layer, which is followed by electroplating copper into the receptacle. In the second method, a copper seed layer is first deposited into a receptacle, a copper composition containing impurities is then electrodeposited into the receptacle and the electronic structure is annealed so that impurities diffuse into the copper seed layer. In the third method, a barrier layer is first deposited into a receptacle, dopant ions are then implanted into the barrier layer with a copper seed layer subsequently deposited on top of the barrier layer. An annealing process for the electronic structure is then carried out such that dopant ions diffuse into the copper seed layer. The present invention method may further include the step of ion-implanting at least one element into a surface layer of the copper conductor after the conductor is first planarized. The surface layer may have a thickness between about 30 Å and about 500 Å. At least one element may be selected from Co, Al, Sn, In, Ti and Cr.

    Abstract translation: 本发明公开了一种在电子结构中形成铜导体的方法，该方法是先将铜组合物沉积在形成于电子结构中的容器中，然后向铜组合物中添加杂质使其电迁移阻力得到改善。 在该方法中，铜组合物可以通过各种技术沉积，例如电镀，物理气相沉积和化学气相沉积。 可植入的杂质包括C，O，Cl，S和N的杂质，其浓度范围为约0.01ppm至约1000ppm。 可以通过三种不同的方法加入杂质。 在第一种方法中，首先将铜种子层沉积到容器中，并在种子层上进行离子注入工艺，然后将铜电镀到容器中。 在第二种方法中，首先将铜种子层沉积到容器中，然后将含有杂质的铜组合物电沉积到容器中，并且将电子结构退火，使得杂质扩散到铜籽晶层中。 在第三种方法中，首先将阻挡层沉积到容器中，然后将掺杂剂离子注入到阻挡层中，随后将铜籽晶层沉积在阻挡层的顶部上。 然后进行电子结构的退火处理，使得掺杂剂离子扩散到铜籽晶层中。 本发明的方法还可以包括在导体首先平坦化之后将至少一种元素离子注入到铜导体的表面层中的步骤。 表面层可以具有在约和之间的厚度。 至少一种元素可以选自Co，Al，Sn，In，Ti和Cr。

Patent Agency Ranking