公开(公告)号：US20060272574A1

公开(公告)日：2006-12-07

申请号：US11147600

申请日：2005-06-07

Applicant: Andrew Waite ,  Scott Luning

Inventor： Andrew Waite ,  Scott Luning

IPC: C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC classification number: H01L29/045 ,  H01L21/76254 ,  H01L21/823807

Abstract: Methods for manufacturing an integrated circuit are provided. An exemplary method comprises the step of providing a silicon substrate having a first crystalline orientation. A silicon layer having a second crystalline orientation is bonded to the silicon substrate. The second crystalline orientation is different from the first crystalline orientation. The silicon layer is etched to expose a portion of the silicon substrate and an amorphous silicon layer is deposited on the exposed portion. The amorphous silicon layer is transformed into a regrown crystalline silicon layer having the first crystalline orientation. A first field effect transistor is formed on the silicon layer and a second field effect transistor is formed on the regrown crystalline silicon layer.

Abstract translation: 提供了制造集成电路的方法。 一种示例性方法包括提供具有第一晶体取向的硅衬底的步骤。 具有第二结晶取向的硅层与硅衬底接合。 第二结晶取向与第一结晶取向不同。 蚀刻硅层以暴露硅衬底的一部分，并且非晶硅层沉积在暴露部分上。 将非晶硅层转变成具有第一晶体取向的再结晶的晶体硅层。 在硅层上形成第一场效应晶体管，在再生晶体硅层上形成第二场效应晶体管。

公开(公告)号：US07138320B2

公开(公告)日：2006-11-21

申请号：US10974232

申请日：2004-10-24

Applicant: Ralf van Bentum ,  Scott Luning ,  Andy Wei

Inventor： Ralf van Bentum ,  Scott Luning ,  Andy Wei

IPC: H01L21/336

CPC classification number: H01L29/66628 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7848 ,  H01L29/78621 ,  H01L29/78687

Abstract: By recessing a semiconductor layer, preferably by locally oxidizing the semiconductor layer, a stress-inducing material and/or a dopant species may be introduced into the thinned semiconductor layer in the vicinity of a gate electrode structure by means of a subsequent epitaxial growth process. In particular, the stress-inducing material formed adjacent to the gate electrode structure exerts compressive or tensile stress, depending on the type of material deposited, thereby also enhancing the mobility of the charge carriers in a channel region of the transistor element.

Abstract translation: 通过优选通过半导体层的局部氧化来凹入半导体层，可以通过随后的外延生长工艺在栅极电极结构附近的薄化半导体层中引入应力诱导材料和/或掺杂物种类。 特别地，与栅电极结构相邻形成的应力诱导材料根据所沉积材料的类型施加压缩或拉伸应力，从而也增强了晶体管元件的沟道区中电荷载流子的迁移率。

公开(公告)号：US06972478B1

公开(公告)日：2005-12-06

申请号：US11075774

申请日：2005-03-07

Applicant: Andrew M. Waite ,  Scott Luning

Inventor： Andrew M. Waite ,  Scott Luning

IPC: H01L21/20 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/78

CPC classification number: H01L29/045 ,  H01L21/2007 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/7833

Abstract: An integrated circuit and methods for its manufacture are provided. The integrated circuit comprises a bulk silicon substrate having a first region of crystalline orientation and a second region of crystalline orientation. A layer of silicon on insulator overlies a portion of the bulk silicon substrate. At least one field effect transistor is formed in the layer of silicon on insulator, at least one P-channel field effect transistor is formed in the second region of crystalline orientation, and at least one N-channel field effect transistor is formed in the first region of crystalline orientation.

Abstract translation: 提供集成电路及其制造方法。 集成电路包括具有<100>晶体取向的第一区域和<110>晶体取向的第二区域的体硅衬底。 绝缘体上的一层覆盖在体硅衬底的一部分上。 在绝缘体上的硅层中形成至少一个场效应晶体管，在<110>晶取向的第二区域中形成至少一个P沟道场效应晶体管，并形成至少一个N沟道场效应晶体管 在<100>晶体取向的第一区域。

公开(公告)号：US06806126B1

公开(公告)日：2004-10-19

申请号：US10236200

申请日：2002-09-06

Applicant: Scott Luning ,  Karsten Wieczorek ,  Thorsten Kammler

Inventor： Scott Luning ,  Karsten Wieczorek ,  Thorsten Kammler

IPC: H01L21338

CPC classification number: H01L29/6659 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  Y10S257/90

Abstract: An insulated gate semiconductor device (100) having reduced gate resistance and a method for manufacturing the semiconductor device (100). A gate structure (112) is formed on a major surface (104) of a semiconductor substrate (102). Successive nitride spacers (118, 128) are formed adjacent the sidewalls of the gate structure (112). The nitride spacers (118, 128) are etched and recessed using a single etch to expose the upper portions (115A, 117A) of the gate structure (112). Source (132) and drain (134) regions are formed in the semiconductor substrate (102). Silicide regions (140, 142, 144) are formed on the top surface (109) and the exposed upper portions (115A, 117A) of the gate structure (112) and the source region (132) and the drain region (134). Electrodes (150, 152, 154) are formed in contact with the silicide (140, 142, 144) of the respective gate structure (112), source region (132), and the drain region (134).

Abstract translation: 一种具有降低的栅极电阻的绝缘栅极半导体器件（100）和用于制造半导体器件（100）的方法。 栅极结构（112）形成在半导体衬底（102）的主表面（104）上。 在栅极结构（112）的侧壁附近形成连续的氮化物间隔物（118,128）。 使用单个蚀刻来蚀刻和凹入氮化物间隔物（118,128）以暴露栅极结构（112）的上部（115A，117A）。 源极（132）和漏极（134）区域形成在半导体衬底（102）中。 在栅极结构（112）和源极区（132）和漏极区（134）的顶表面（109）和暴露的上部（115A，117A）上形成硅化物区域（140,142,144）。 电极（150,152,154）形成为与相应的栅极结构（112），源极区（132）和漏极区（134）的硅化物（140,142,144）接触。

公开(公告)号：US06548335B1

公开(公告)日：2003-04-15

申请号：US09651891

申请日：2000-08-30

Applicant: Carl Robert Huster ,  Concetta Riccobene ,  Scott Luning

Inventor： Carl Robert Huster ,  Concetta Riccobene ,  Scott Luning

IPC: H01L21336

CPC classification number: H01L29/66651 ,  H01L21/28167 ,  H01L21/28211

Abstract: Channel carrier mobility is increased by reducing gate/gate dielectric interface roughness, thereby reducing surface scattering. Embodiments include depositing a layer of silicon by selective epitaxy prior to gate oxide formation to provide a substantially atomically smooth surface resulting in a smoother interface between the gate polysilicon and silicon oxide after oxidation.

Abstract translation: 通过减少栅极/栅极电介质界面粗糙度从而减小表面散射，增加沟道载流子迁移率。 实施例包括在栅极氧化物形成之前通过选择性外延沉积硅层以提供基本上原子上平滑的表面，导致在氧化后栅极多晶硅和氧化硅之间的平滑的界面。

公开(公告)号：US06440819B1

公开(公告)日：2002-08-27

申请号：US09034100

申请日：1998-03-03

Applicant: Scott Luning

Inventor： Scott Luning

IPC: H01L2176

CPC classification number: H01L21/76221

Abstract: A local oxidation of silicon (LOCOS) process directed to forming differential field oxide thickness on a single wafer with minimized process steps and optimized planarity. When patterning the masking layer, at least two window widths are formed in the masking layer, exposing the underlying substrate and pad oxide. When one of the window widths is sufficiently small, oxidation of the substrate will be inhibited causing reduced growth and thus a reduced field oxide thickness in that window as compared to other larger windows formed in the same masking layer, creating differential field oxide thicknesses in one growth step. To optimize planarity, prior to oxidation variable depth trenches are formed in alignment with the windows so that the resulting field oxide regions are substantially planar with the substantial surface.

Abstract translation: 硅的局部氧化（LOCOS）工艺旨在以最小化的工艺步骤和优化的平面性在单个晶片上形成差分场氧化物厚度。 当图案化掩模层时，在掩模层中形成至少两个窗口宽度，暴露下面的衬底和衬垫氧化物。 当窗口宽度之一足够小时，与在相同掩模层中形成的其它较大窗口相比，衬底的氧化将被抑制，导致生长减小并且因此减小了该窗口中的场氧化物厚度，从而在一个窗口中产生差异的场氧化物厚度 成长步骤 为了优化平面性，在氧化之前，可变深度沟槽形成为与窗口对准，使得所得到的场氧化物区域与实质表面基本上是平面的。

公开(公告)号：US5854132A

公开(公告)日：1998-12-29

申请号：US346041

申请日：1994-11-29

Applicant: Shekhar Pramanick ,  Scott Luning ,  Jonathon Fewkes

Inventor： Shekhar Pramanick ,  Scott Luning ,  Jonathon Fewkes

IPC: G03F7/09 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/465

CPC classification number: G03F7/091 ,  H01L21/0276 ,  H01L21/32137

Abstract: A method for patterning a polysilicon layer includes creating a TiN layer above an amorphous silicon (a-Si) layer forming a TiN/a-Si stack. The TiN/a-Si stack is formed above the polysilicon layer. The TiN layer serves as an ARC to reduce overexposure of the photoresist used to pattern the polysilicon layer, while the a-Si layer prevents contamination of the layer below the polysilicon layer.

Abstract translation: 用于图案化多晶硅层的方法包括在形成TiN / a-Si叠层的非晶硅（a-Si）层上方形成TiN层。 在多晶硅层上形成TiN / a-Si叠层。 TiN层用作ARC以减少用于图案化多晶硅层的光致抗蚀剂的过度曝光，而a-Si层防止多晶硅层下面的层被污染。

公开(公告)号：US5652447A

公开(公告)日：1997-07-29

申请号：US684920

申请日：1996-07-22

Applicant: Jian Chen ,  Yuan Tang ,  Scott Luning ,  Salvatore F. Cagnina

Inventor： Jian Chen ,  Yuan Tang ,  Scott Luning ,  Salvatore F. Cagnina

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  G11C11/34 ,  H01L29/76

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A flash EEPROM having reduced column leakage current suitably includes cells with more uniform erase times arranged in an array. An intermediate n+ implant immediately following the DDI implant step suitably provides an enhanced doping profile in the tunneling region, which increases the rate at which F-N tunneling occurs to erase the cells, and which increases the uniformity of F-N tunneling rates among memory cells within the array. A thermal cycle drives the intermediate n+ implant deeper into the tunneling region. Alternatively, an n+ implant may be performed at a relatively large angle with respect to the semiconductor substrate, which improves the doping concentration in the tunneling region of the source.

Abstract translation: 具有降低的列泄漏电流的快闪EEPROM适当地包括以阵列布置的更均匀擦除次数的单元。 紧接在DDI注入步骤之后的中间n +注入适当地提供隧道区域中的增强的掺杂分布，这增加了发生FN隧道以擦除单元的速率，并且这增加阵列内的存储单元之间的FN隧穿速率的均匀性 。 热循环驱动中间n +植入物更深入隧道区域。 或者，可以相对于半导体衬底以相对大的角度执行n +注入，这改善了源极的隧道区域中的掺杂浓度。

公开(公告)号：US5482881A

公开(公告)日：1996-01-09

申请号：US403460

申请日：1995-03-14

Applicant: Jian Chen ,  Yuan Tang ,  Scott Luning ,  Salvatore F. Cagnina

Inventor： Jian Chen ,  Yuan Tang ,  Scott Luning ,  Salvatore F. Cagnina

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A flash EEPROM having reduced column leakage current suitably includes cells with more uniform erase times arranged in an array. An intermediate n+ implant immediately following the DDI implant step suitably provides an enhanced doping profile in the tunneling region, which increases the rate at which F-N tunneling occurs to erase the cells, and which increases the uniformity of F-N tunneling rates among memory cells within the array. A thermal cycle drives the intermediate n+ implant deeper into the tunneling region. Alternatively, an n+ implant may be performed at a relatively large angle with respect to the semiconductor substrate, which improves the doping concentration in the tunneling region of the source.

Abstract translation: 具有降低的列泄漏电流的快闪EEPROM适当地包括以阵列布置的更均匀擦除次数的单元。 紧接在DDI注入步骤之后的中间n +注入适当地提供隧道区域中的增强的掺杂分布，这增加了发生FN隧道以擦除单元的速率，并且这增加阵列内的存储单元之间的FN隧穿速率的均匀性 。 热循环驱动中间n +植入物更深入隧道区域。 或者，可以相对于半导体衬底以相对大的角度执行n +注入，这改善了源极的隧道区域中的掺杂浓度。

公开(公告)号：US08120120B2

公开(公告)日：2012-02-21

申请号：US12561685

申请日：2009-09-17

Applicant: Frank (Bin) Yang ,  Johan W. Weijtmans ,  Scott Luning

Inventor： Frank (Bin) Yang ,  Johan W. Weijtmans ,  Scott Luning

IPC: H01L29/772 ,  H01L21/335

CPC classification number: H01L29/665 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: Semiconductor devices with embedded silicon germanium source/drain regions are formed with enhanced channel mobility, reduced contact resistance, and reduced silicide encroachment. Embodiments include embedded silicon germanium source/drain regions with a first portion having a relatively high germanium concentration, e.g., about 25 to about 35 at. %, an overlying second portion having a first layer with a relatively low germanium concentration, e.g., about 10 to about 20 at. %, and a second layer having a germanium concentration greater than that of the first layer. Embodiments include forming additional layers on the second layer, each odd numbered layer having relatively low germanium concentration, at. % germanium, and each even numbered layer having a relatively high germanium concentration. Embodiments include forming the first region at a thickness of about 400 Å to 28 about 800 Å, and the first and second layers at a thickness of about 30 Å to about 70 Å.

Abstract translation: 具有嵌入式硅锗源极/漏极区域的半导体器件形成具有增强的沟道迁移率，降低的接触电阻和减少的硅化物侵蚀。 实施例包括具有较高锗浓度的第一部分的嵌入式硅锗源/漏区，例如约25至约35at。 ％，上覆的第二部分具有具有相对低的锗浓度的第一层，例如约10至约20at。 ％，第二层的锗浓度大于第一层的浓度。 实施例包括在第二层上形成附加层，每个奇数层具有较低的锗浓度。 ％锗，并且每个偶数层具有较高的锗浓度。 实施例包括形成厚度为约400至28约800的第一区域，第一和第二层的厚度为约至大约为70埃。