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    Selective epitaxy to reduce gate/gate dielectric interface roughness
    1.
    发明授权
    Selective epitaxy to reduce gate/gate dielectric interface roughness 失效
    选择性外延以减少栅极/栅极电介质界面粗糙度

    公开(公告)号：US06548335B1

    公开(公告)日：2003-04-15

    申请号：US09651891

    申请日：2000-08-30

    申请人： Carl Robert Huster ,  Concetta Riccobene ,  Scott Luning

    发明人： Carl Robert Huster ,  Concetta Riccobene ,  Scott Luning

    IPC分类号： H01L21336

    CPC分类号： H01L29/66651 ,  H01L21/28167 ,  H01L21/28211

    摘要： Channel carrier mobility is increased by reducing gate/gate dielectric interface roughness, thereby reducing surface scattering. Embodiments include depositing a layer of silicon by selective epitaxy prior to gate oxide formation to provide a substantially atomically smooth surface resulting in a smoother interface between the gate polysilicon and silicon oxide after oxidation.

    摘要翻译： 通过减少栅极/栅极电介质界面粗糙度从而减小表面散射，增加沟道载流子迁移率。 实施例包括在栅极氧化物形成之前通过选择性外延沉积硅层以提供基本上原子上平滑的表面，导致在氧化后栅极多晶硅和氧化硅之间的平滑的界面。

    MOSFET with asymmetrical extension implant
    2.
    发明授权
    MOSFET with asymmetrical extension implant 有权
    具有不对称延伸植入物的MOSFET

    公开(公告)号：US08193592B2

    公开(公告)日：2012-06-05

    申请号：US12904662

    申请日：2010-10-14

    申请人： Frank Bin Yang ,  Andrew M. Waite ,  Scott Luning

    发明人： Frank Bin Yang ,  Andrew M. Waite ,  Scott Luning

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L21/26586 ,  H01L29/66659 ,  H01L29/7834 ,  H01L2924/0002 ,  Y10S438/931 ,  H01L2924/00

    摘要： A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with respect to the gate structure. An ion implantation process is performed at a non-zero tilt angle. At least one spacer and the gate electrode mask a portion of the surface during the ion implantation process such that the source extension and drain extension are asymmetrically positioned with respect to the gate structure by an asymmetry measure.

    摘要翻译： 一种用于制造MOSFET（例如，PMOS FET）的方法包括提供具有由（110）表面取向或（110）侧壁表面表征的表面的半导体衬底，在表面上形成栅极结构，并形成源延伸和 半导体衬底中的漏极延伸部相对于栅极结构非对称地定位。 以非零倾角进行离子注入工艺。 在离子注入过程期间，至少一个间隔物和栅电极掩盖表面的一部分，使得源极延伸和漏极延伸通过不对称度量相对于栅极结构不对称地定位。

    Stressed field effect transistor and methods for its fabrication
    3.
    发明授权
    Stressed field effect transistor and methods for its fabrication 有权
    强调场效应晶体管及其制造方法

    公开(公告)号：US08148214B2

    公开(公告)日：2012-04-03

    申请号：US12360961

    申请日：2009-01-28

    申请人： Andrew M. Waite ,  Scott Luning

    发明人： Andrew M. Waite ,  Scott Luning

    IPC分类号： H01L21/00

    CPC分类号： H01L29/6656 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

    摘要： A stressed field effect transistor and methods for its fabrication are provided. The field effect transistor comprises a silicon substrate with a gate insulator overlying the silicon substrate. A gate electrode overlies the gate insulator and defines a channel region in the silicon substrate underlying the gate electrode. A first silicon germanium region having a first thickness is embedded in the silicon substrate and contacts the channel region. A second silicon germanium region having a second thickness greater than the first thickness and spaced apart from the channel region is also embedded in the silicon substrate.

    摘要翻译： 提供了一种应力场效应晶体管及其制造方法。 场效应晶体管包括具有覆盖硅衬底的栅极绝缘体的硅衬底。 栅电极覆盖栅极绝缘体，并且在栅电极下面的硅衬底中限定沟道区。 具有第一厚度的第一硅锗区域嵌入在硅衬底中并与沟道区域接触。 具有大于第一厚度并且与沟道区间隔开的第二厚度的第二硅锗区域也嵌入在硅衬底中。

    EMBEDDED SILICON GERMANIUM SOURCE DRAIN STRUCTURE WITH REDUCED SILICIDE ENCROACHMENT AND CONTACT RESISTANCE AND ENHANCED CHANNEL MOBILITY
    4.
    发明申请
    EMBEDDED SILICON GERMANIUM SOURCE DRAIN STRUCTURE WITH REDUCED SILICIDE ENCROACHMENT AND CONTACT RESISTANCE AND ENHANCED CHANNEL MOBILITY 有权
    嵌入式硅锗锗排水结构，具有降低的硅胶密封性和接触电阻和增强的通道移动性

    公开(公告)号：US20110062498A1

    公开(公告)日：2011-03-17

    申请号：US12561685

    申请日：2009-09-17

    申请人： Frank (Bin) Yang ,  Johan W. Weijtmans ,  Scott Luning

    发明人： Frank (Bin) Yang ,  Johan W. Weijtmans ,  Scott Luning

    IPC分类号： H01L29/772 ,  H01L21/335

    CPC分类号： H01L29/665 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

    摘要： Semiconductor devices with embedded silicon germanium source/drain regions are formed with enhanced channel mobility, reduced contact resistance, and reduced silicide encroachment. Embodiments include embedded silicon germanium source/drain regions with a first portion having a relatively high germanium concentration, e.g., about 25 to about 35 at. %, an overlying second portion having a first layer with a relatively low germanium concentration, e.g., about 10 to about 20 at. %, and a second layer having a germanium concentration greater than that of the first layer. Embodiments include forming additional layers on the second layer, each odd numbered layer having relatively low germanium concentration, at. % germanium, and each even numbered layer having a relatively high germanium concentration. Embodiments include forming the first region at a thickness of about 400 Å to 28 about 800 Å, and the first and second layers at a thickness of about 30 Å to about 70 Å.

    摘要翻译： 具有嵌入式硅锗源极/漏极区域的半导体器件形成具有增强的沟道迁移率，降低的接触电阻和减少的硅化物侵蚀。 实施例包括具有较高锗浓度的第一部分的嵌入式硅锗源/漏区，例如约25至约35at。 ％，上覆的第二部分具有具有相对低的锗浓度的第一层，例如约10至约20at。 ％，第二层的锗浓度大于第一层的浓度。 实施例包括在第二层上形成附加层，每个奇数层具有较低的锗浓度。 ％锗，并且每个偶数层具有较高的锗浓度。 实施例包括形成厚度为约400至28约800的第一区域，第一和第二层的厚度为约至大约为70埃。

    Stacking fault reduction in epitaxially grown silicon
    5.
    发明授权
    Stacking fault reduction in epitaxially grown silicon 有权
    堆积外延生长硅中的断层减少

    公开(公告)号：US07893493B2

    公开(公告)日：2011-02-22

    申请号：US11456326

    申请日：2006-07-10

    申请人： Yun-Yu Wang ,  Linda Black ,  Judson R. Holt ,  Woo-Hyeong Lee ,  Scott Luning ,  Christopher D. Sheraw

    发明人： Yun-Yu Wang ,  Linda Black ,  Judson R. Holt ,  Woo-Hyeong Lee ,  Scott Luning ,  Christopher D. Sheraw

    IPC分类号： H01L27/12 ,  H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/02639 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/84

    摘要： An intermediate hybrid surface orientation structure may include a silicon-on-insulator (SOI) substrate adhered to a bulk silicon substrate, the silicon of the SOI substrate having a different surface orientation than that of the bulk silicon substrate, and a reachthrough region extending through the SOI substrate to the bulk silicon substrate, the reachthrough region including a silicon nitride liner over a silicon oxide liner and a silicon epitaxially grown from the bulk silicon substrate, the epitaxially grown silicon extending into an undercut into the silicon oxide liner under the silicon nitride liner, wherein the epitaxially grown silicon is substantially stacking fault free.

    摘要翻译： 中间混合表面取向结构可以包括粘附到体硅衬底上的绝缘体上硅（SOI）衬底，SOI衬底的硅具有与体硅衬底不同的表面取向，并且穿透区域延伸穿过 SOI衬底到体硅衬底，穿透区域包括在氧化硅衬底上的氮化硅衬垫和从体硅衬底外延生长的硅，外延生长的硅延伸到底切到氮化硅之下的氧化硅衬底中 衬垫，其中外延生长的硅基本上是无层错的。

    Differential implant oxide process
    10.
    发明授权
    Differential implant oxide process 有权
    差分植入氧化物工艺

    公开(公告)号：US06821853B1

    公开(公告)日：2004-11-23

    申请号：US10159413

    申请日：2002-05-31

    申请人： James F. Buller ,  Scott Luning

    发明人： James F. Buller ,  Scott Luning

    IPC分类号： H01L218234

    CPC分类号： H01L21/823468 ,  H01L21/823462

    摘要： Methods of manufacturing are provided. In one aspect, a method of manufacturing is provided that includes forming first and second gate stacks on a substrate and forming an insulating layer on the substrate. The insulating layer has portions adjacent to the first stack and portions adjacent to the second gate stack. A first pair of insulating structures is formed adjacent to the first gate stack and a second pair of insulating structures is formed adjacent to the second gate stack. The first pair of insulating structures is removed. The portions of the insulating layer adjacent to the first gate stack are thickened while the second pair of insulating structures prevents thickening of the portions of the insulating film adjacent to the second gate stack. Differential insulating layer thickness for different gate devices is permitted to enable reduction in leakage currents for selected devices without harming speed performance for others.

    摘要翻译： 提供制造方法。 一方面，提供一种制造方法，其包括在衬底上形成第一和第二栅极叠层并在衬底上形成绝缘层。 绝缘层具有与第一堆叠相邻的部分和与第二栅极堆叠相邻的部分。 第一对绝缘结构形成为与第一栅极堆叠相邻，并且第二对绝缘结构形成为与第二栅极堆叠相邻。 第一对绝缘结构被去除。 与第一栅极堆叠相邻的绝缘层的部分被加厚，而第二对绝缘结构防止绝缘膜的与第二栅极叠层相邻的部分的增厚。 允许不同栅极器件的差分绝缘层厚度能够减少所选器件的漏电流，而不会损害其他器件的速度性能。