-
21.发明授权公开(公告)号：US11380644B2
公开(公告)日：2022-07-05
申请号：US16917155
申请日：2020-06-30
Inventor： Feng Qin , Kerui Xi , Tingting Cui , Jie Zhang , Xuhui Peng
Abstract: Provided are a semiconductor package and a method for fabricating the semiconductor package. The method includes followings steps: a first workpiece is provided, where the first workpiece includes a first substrate and multiple first rewiring structures arranged on the first substrate at intervals, and each first rewiring structure includes at least two first rewiring layers; an encapsulation layer is formed on the first rewiring structures, where the encapsulation layer is provided with multiple first through holes, and the first through holes exposes one first rewiring layer; at least two second rewiring layers are disposed on a side of the encapsulation layer facing away from the first rewiring layer; multiple semiconductor elements are provided, where the semiconductor elements are arranged on a side of the first rewiring structures facing away from the encapsulation layer, where the first rewiring layers are electrically connected to pins of the semiconductor elements.
-
公开(公告)号：US11257765B2
公开(公告)日：2022-02-22
申请号：US16441501
申请日：2019-06-14
Applicant: Shanghai AVIC OPTO Electronics Co., Ltd.
IPC: H01L23/538 , H01L21/48 , H01L21/56 , H01L23/31 , H01L23/00
Abstract: Chip package structure and chip package method are provided. The chip package structure includes an encapsulating layer, a redistribution layer, a soldering pad group, and bare chips. Connecting posts is formed on a side of the bare chips. The encapsulating layer covers the bare chips and the connecting posts, while exposes a side of the connecting posts away from the bare chips. The redistribution layer on the connecting posts includes a first redistribution wire, a second redistribution wire, and a third redistribution wire. The first redistribution wire and the second redistribution wire are electrically connected to at least one connecting post respectively, and the third redistribution layer is electrically connected to remaining connecting posts. The soldering pad group on the redistribution layer includes an input soldering pad electrically connected to the first redistribution wire and an output soldering pad electrically connected to the second redistribution wire.
-
公开(公告)号：US11764181B2
公开(公告)日：2023-09-19
申请号：US17829619
申请日：2022-06-01
Inventor： Feng Qin , Kerui Xi , Tingting Cui , Jie Zhang , Xuhui Peng
CPC classification number: H01L24/19 , H01L21/561 , H01L23/3121 , H01L24/11 , H01L24/13 , H01L24/20 , H01L24/81 , H01L24/96 , H01L24/97 , H01L2224/2101 , H01L2924/37001
Abstract: Provided are a semiconductor package and a method for fabricating the semiconductor package. The method includes the followings steps: a first workpiece is provided, where the first workpiece includes a first substrate and multiple first rewiring structures arranged on the first substrate at intervals, and each first rewiring structure includes at least two first rewiring layers; an encapsulation layer is formed on the first rewiring structures, where the encapsulation layer is provided with multiple first through holes, and the first through holes expose one first rewiring layer; at least two second rewiring layers are disposed on a side of the encapsulation layer facing away from the first rewiring layer; multiple semiconductor elements are provided, where the semiconductor elements are arranged on a side of the first rewiring structures facing away from the encapsulation layer, where the first rewiring layers are electrically connected to pins of the semiconductor elements.
-
公开(公告)号：US11458842B2
公开(公告)日：2022-10-04
申请号：US17016776
申请日：2020-09-10
Applicant: Shanghai AVIC OPTO Electronics Co., Ltd.
Abstract: Provided are a display panel and a vehicle. The display device includes a knob and a main display panel; the knob includes a first magnetic adhering piece; the display device further includes a second magnetic adhering structure, and the second magnetic adhering structure is disposed on a non-light exiting side of the main display panel; the second magnetic adhering structure includes a plurality of first magnetic adhering regions, and at least two first magnetic adhering regions are not overlapped; when the knob is magnetically adhered to any one of the plurality of first magnetic adhering regions, the knob is disposed on a light exiting side of the main display panel.
-
公开(公告)号：US20220077596A1
公开(公告)日：2022-03-10
申请号：US17530425
申请日：2021-11-18
Inventor： Kerui Xi , Xuhui Peng , Feng Qin , Tingting Cui , Zhenyu Jia
Abstract: Disclosed antenna unit includes first substrate and second substrate opposite to each other, phase shifting units and driver circuit. Region facing the first substrate and the second substrate form phase shifting region. In first direction, the first substrate formed with first step region, and used for connecting radio-frequency signal terminal; in second direction, the second substrate formed with second step region, and included angle between the first direction and the second direction greater than or equal to 0° and smaller than 180°. At least part of the first step region does not overlap at least part of the second step region. Phase shifting units used for radiating radio-frequency signal and distributed in phase shifting region, each phase shifting unit. At least part of the driver circuit disposed in the second step region and the driver circuit electrically connected to each phase shifting unit to adjust radio-frequency signal.
-
Patent Agency Ranking
公开(公告)号：US20210351150A1
公开(公告)日：2021-11-11
申请号：US16917155
申请日：2020-06-30
Inventor： Feng Qin , Kerui Xi , Tingting Cui , Jie Zhang , Xuhui Peng
Abstract: Provided are a semiconductor package and a method for fabricating the semiconductor package. The method includes followings steps: a first workpiece is provided, where the first workpiece includes a first substrate and multiple first rewiring structures arranged on the first substrate at intervals, and each first rewiring structure includes at least two first rewiring layers; an encapsulation layer is formed on the first rewiring structures, where the encapsulation layer is provided with multiple first through holes, and the first through holes exposes one first rewiring layer; at least two second rewiring layers are disposed on a side of the encapsulation layer facing away from the first rewiring layer; multiple semiconductor elements are provided, where the semiconductor elements are arranged on a side of the first rewiring structures facing away from the encapsulation layer, where the first rewiring layers are electrically connected to pins of the semiconductor elements.
-
公开(公告)号：US11103869B2
公开(公告)日：2021-08-31
申请号：US16444282
申请日：2019-06-18
Applicant: Shanghai AVIC OPTO Electronics Co., Ltd.
Inventor： Kerui Xi , Feng Qin , Jine Liu , Xiaohe Li , Tingting Cui
IPC: B01L3/00
Abstract: A microfluidic chip, a method for driving a microfluidic chip and an analysis apparatus are provided. An exemplary microfluidic chip includes a substrate; a number of M driving electrodes disposed on a side of the substrate and arranged along a first direction; and a number of N signal terminals electrically connected to the number of M driving electrodes. Any three adjacent driving electrodes are connected to different signal terminals, respectively; a number of A of the number of M driving electrodes are connected to a same signal terminal; and M, N and A are positive integers, and M≥4, N≥3, M>N, and A≥2.
-
公开(公告)号：US11048132B2
公开(公告)日：2021-06-29
申请号：US16942786
申请日：2020-07-30
Applicant: Shanghai AVIC OPTO Electronics Co., Ltd.
Inventor： Shoufu Jian , Feng Qin , Dandan Qin , Benshun Zhong
IPC: G02F1/1362 , G02F1/1345 , G02F1/1368
Abstract: Provided are a display panel and a display apparatus. The display panel has a bonding region where a chip is bonded, and a fan-out region where fan-out leads is arranged. Bonding pads in the bonding region include a first pad array and a second pad array, the first pad array being at a side of the second pad array close to the display region. The first pad array includes first pads arranged in at least two rows. The first pad array includes at least one inclined section including at least three first pads that are arranged sequentially and obliquely away from the display region. Such an arrangement allows at least a portion of the fan-out leads to be displaced into the bonding region, to increase the area for arranging the fan-out leads. Therefore, the lower border of the display panel is narrowed.
-
公开(公告)号：US10989973B2
公开(公告)日：2021-04-27
申请号：US16533634
申请日：2019-08-06
Applicant: Shanghai AVIC OPTO Electronics Co., Ltd.
IPC: G02F1/1362 , B33Y30/00 , B29C64/286 , G02F1/1339 , G02F1/1368 , H01L27/12
Abstract: A 3D printed display panel includes two opposing substrates and a black matrix formed on one of the substrates. The light proof areas of the black matrix include multiple first portions, multiple second portions and multiple third portions arranged to form a grid structure. The first portions and the third portions are alternately arranged in a direction of the scanning lines, the second portions and the third portions are alternately arranged in a direction of the data lines. Meshes of the grid structure are aperture zones of the black matrix. The aperture zones are in one-to-one correspondence with the pixel units. A vertical projections of the scanning lines and the data lines on the second substrate are located in the lightproof areas; where a minimum width of one first portion is X, a minimum width of one second portion is Y, and |X−Y|≤2 μm.
-
30.发明授权公开(公告)号：US10790225B1
公开(公告)日：2020-09-29
申请号：US16441243
申请日：2019-06-14
Applicant: Shanghai AVIC OPTO Electronics Co., Ltd.
Inventor： Kerui Xi , Feng Qin , Jine Liu , Xiaohe Li , Tingting Cui , Xuhui Peng
IPC: H01L23/522 , H01L23/31 , H01L21/56 , H01L49/02 , H01L25/16 , H01L23/528
Abstract: Chip package structure and chip package method are provided. The chip package structure includes an encapsulating layer, a first metal layer, a second metal layer, and bare chips. The bare chips include first bare chips and second bare chips. First-connecting-posts are formed on a side of the first bare chips and on a side of the second bare chips. The encapsulating layer covers the bare chips and the first-connecting-posts. The first metal layer is disposed on the side of the first-connecting-posts away from the bare chips and includes first capacitor polar plates and conductive parts. The first capacitor polar plates are electrically connected to the first-connecting-posts on the first bare chips, and the conductive parts are electrically connected to the first-connecting-posts on the second bare chips. The second metal layer is disposed on a side of the first metal layer away from the encapsulating layer and includes second capacitor polar plates electrically connected to the conductive parts.
-
-
-
-
-
-
-
-
-
Search Results
32
records
(took 0.018 seconds)
