公开(公告)号：US20200043955A1

公开(公告)日：2020-02-06

申请号：US16515057

申请日：2019-07-18

Applicant: Sharp Kabushiki Kaisha

Inventor： Masahiko SUZUKI ,  Tohru DAITOH ,  Hajime IMAI ,  Tetsuo KIKUCHI ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Masamitsu YAMANAKA ,  Kengo HARA

IPC: H01L27/12 ,  G02F1/1368 ,  G02F1/1362

Abstract: A semiconductor device includes a first TFT, a first source-side connection section that is formed from a part of a second metal film and connected to a first source region, a first drain-side connection section that is formed from a part of the second metal film and connected to a first drain region, a second TFT that is driven by the first TFT, a second source-side connection section that is formed from a part of a first metal film and connected to a second source region, and a second drain-side connection section that is formed from a part of the first metal film or a second transparent electrode film and connected to a second drain region.

公开(公告)号：US20200035717A1

公开(公告)日：2020-01-30

申请号：US16508603

申请日：2019-07-11

Applicant: Sharp Kabushiki Kaisha

Inventor： Kengo HARA ,  Tohru DAITOH ,  Hajime IMAI ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Masamitsu YAMANAKA

IPC: H01L27/12 ,  H01L29/786

Abstract: A thin film transistor substrate includes a source line, a gate electrode, a channel region, a source region, a drain region, and a pixel electrode. The gate electrode is a portion of a first metal film disposed upper than a first insulating film that is disposed upper than a semiconductor film. The source line is a portion of a second metal film disposed upper than a second insulating film that is disposed upper than the first metal film. The channel region is a portion of a section of the semiconductor film and disposed to overlap the gate electrode. The source region is prepared by reducing a resistance of a section of the semiconductor film. The drain region is prepared by reducing a resistance of a section of the semiconductor film. The pixel electrode is prepared by reducing a resistance of a section of the semiconductor film.

公开(公告)号：US20200027958A1

公开(公告)日：2020-01-23

申请号：US16497893

申请日：2018-03-23

Applicant: Sharp Kabushiki Kaisha

Inventor： Masahiko SUZUKI ,  Hideki KITAGAWA ,  Tetsuo KIKUCHI ,  Toshikatsu ITOH ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Kengo HARA ,  Hajime IMAI ,  Tohru DAITOH

IPC: H01L29/49 ,  G02F1/1368 ,  H01L27/12 ,  H01L29/24 ,  H01L29/51 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: An active matrix substrate according to an embodiment of the present invention includes a plurality of thin film transistors supported on a substrate and an inorganic insulating layer covering the plurality of thin film transistors. Each thin film transistor includes a gate electrode, an oxide semiconductor layer, a gate insulating layer, a source electrode, and a drain electrode. At least one of the gate insulating layer and the inorganic insulating layer is an insulating layer stack having a multilayer structure including a silicon oxide layer and a silicon nitride layer. The insulating layer stack further includes an intermediate layer disposed between the silicon oxide layer and the silicon nitride layer, the intermediate layer having a refractive index nC higher than a refractive index nA of the silicon oxide layer and lower than a refractive index nB of the silicon nitride layer.

公开(公告)号：US20200020756A1

公开(公告)日：2020-01-16

申请号：US16496969

申请日：2018-03-19

Applicant: Sharp Kabushiki Kaisha

Inventor： Teruyuki UEDA ,  Hideki KITAGAWA ,  Tohru DAITOH ,  Hajime IMAI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Tetsuo KIKUCHI ,  Toshikatsu ITOH ,  Kengo HARA

IPC: H01L27/32 ,  G02F1/1362

Abstract: An oxide semiconductor TFT (201) of an active matrix substrate includes an oxide semiconductor layer (107), an upper gate electrode (112) disposed on a part of the oxide semiconductor layer via a gate insulating layer, and a source electrode (113) and a drain electrode (114). As viewed from a normal direction of the substrate, the oxide semiconductor layer (107) includes a first portion (p1) that overlaps the upper gate electrode, and a second portion (p2) that is located between the first portion and the source contact region or drain contact region, such that the gate insulating layer does not cover the second portion. The upper gate electrode (112) has a multilayer structure including an alloy layer (112L) that is in contact with the gate insulating layer and a metal layer (112U) that is disposed on the alloy layer. The metal layer is made of a first metallic element M; the alloy layer is made of an alloy containing the first metallic element M; and the first metallic element M is Cu, Mo, or Cr.

公开(公告)号：US20190113789A1

公开(公告)日：2019-04-18

申请号：US16161114

申请日：2018-10-16

Applicant: Sharp Kabushiki Kaisha

Inventor： Toshikatsu ITOH ,  Tohru DAITOH ,  Hajime IMAI ,  Masaki MAEDA ,  Hideki KITAGAWA ,  Yoshihito HARA ,  Tatsuya KAWASAKI

IPC: G02F1/1333 ,  H01L27/12 ,  H01L21/3213 ,  G02F1/1343 ,  G02F1/1362

Abstract: A method of manufacturing a display panel substrate includes a transparent conductive film formation step of forming a transparent conductive film on a flattening film that covers a switching component disposed on a substrate, a metallic film formation step of forming a metallic film so as to cover the transparent conductive film after the transparent conductive film formation step, a line formation step of forming a line by etching the metallic film after the metallic film formation step, and a transparent electrode formation step of forming a transparent electrode that is connected to the line by etching the transparent conductive film after the wire formation step.

公开(公告)号：US20140197412A1

公开(公告)日：2014-07-17

申请号：US14215338

申请日：2014-03-17

Applicant: Sharp Kabushiki Kaisha

Inventor： Jun NISHIMURA ,  Hideki KITAGAWA ,  Atsuhito MURAI ,  Hajime IMAI ,  Shinya TANAKA ,  Mitsunori IMADE ,  Tetsuo KIKUCHI ,  Junya SHIMADA ,  Kazunori MORIMOTO

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L29/78663 ,  G02F1/13338 ,  G02F1/13624 ,  G06F3/0412 ,  H01L27/0207 ,  H01L27/0705 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1251 ,  H01L29/78633 ,  H01L29/7869

Abstract: A source and drain electrode layer (3s/3d) of an oxide TFT element (3) is formed by a first conductive layer. A gate electrode (3g) of the oxide TFT element (3) and a gate electrode (5g) of an a-Si TFT element (5) are formed by a single conductive layer, that is, a second conductive layer. A source and drain electrode layer (5s/5d) of the a-Si TFT element (5) is formed by a third conductive layer. The third conductive layer is formed above the second conductive layer in a thickness direction in which each conductive layer is stacked on an insulating substrate (2). Further, the first conductive layer is formed below the second conductive layer in the thickness direction. Therefore, it is possible to provide a circuit board that can have an improved degree of integration of transistor elements formed on the insulating substrate.

Abstract translation: 氧化物TFT元件（3）的源极和漏极电极层（3s / 3d）由第一导电层形成。 氧化物TFT元件（3）的栅极（3g）和a-Si TFT元件（5）的栅电极（5g）由单个导电层即第二导电层形成。 a-Si TFT元件（5）的源极和漏极电极层（5s / 5d）由第三导电层形成。 第三导电层形成在第二导电层上方的厚度方向上，其中每个导电层堆叠在绝缘基板（2）上。 此外，第一导电层在厚度方向上形成在第二导电层的下方。 因此，可以提供可以使形成在绝缘基板上的晶体管元件的集成度提高的电路板。

公开(公告)号：US20220157855A1

公开(公告)日：2022-05-19

申请号：US17665750

申请日：2022-02-07

Applicant: Sharp Kabushiki Kaisha

Inventor： Hajime IMAI ,  Tohru DAITOH ,  Tetsuo KIKUCHI ,  Masamitsu YAMANAKA ,  Yoshihito HARA ,  Tatsuya KAWASAKI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA

IPC: H01L27/12 ,  H01L29/24 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/465 ,  H01L29/66 ,  G02F1/1368 ,  G02F1/1362 ,  G02F1/1343

Abstract: The oxide semiconductor layer is electrically connected to a source electrode or the source bus line within the source opening formed in the lower insulating layer, each wiring line connection section includes a lower conductive portion formed using the first conductive film, the lower insulating layer extending over the lower conductive portion, an oxide connection layer formed using an oxide film the same as the oxide semiconductor layer and electrically connected to the lower conductive portion within the lower opening formed in the lower insulating layer, an insulating layer covering the oxide connection layer, and an upper conductive portion electrically connected to the oxide connection layer within the upper opening formed in the insulating layer, wherein the oxide connection layer includes a region lower in a specific resistance than the channel region of the oxide semiconductor layer.

公开(公告)号：US20220077318A1

公开(公告)日：2022-03-10

申请号：US17524766

申请日：2021-11-12

Applicant: Sharp Kabushiki Kaisha

Inventor： Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Masamitsu YAMANAKA ,  Tohru DAITOH ,  Hajime IMAI ,  Kengo HARA

IPC: H01L29/786 ,  H01L29/417 ,  G02F1/1368 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66

Abstract: A semiconductor device includes a thin film transistor, wherein: a semiconductor layer of the thin film transistor has a layered structure including a lower oxide semiconductor layer including In, Ga, Zn and Sn and an upper oxide semiconductor layer arranged on the lower oxide semiconductor layer and including In, Ga and Zn; a thickness of the lower oxide semiconductor layer is 20 nm or less; an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer is 5% or more; the upper oxide semiconductor layer includes no Sn, or an atomic ratio of Sn with respect to all metal elements of the upper oxide semiconductor layer is smaller than an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer; and a first angle θ1 between a side surface and a lower surface of the lower oxide semiconductor layer is smaller than a second angle θ2 between a side surface and a lower surface of the upper oxide semiconductor layer.

公开(公告)号：US20210390920A1

公开(公告)日：2021-12-16

申请号：US17401396

申请日：2021-08-13

Applicant: Sharp Kabushiki Kaisha

Inventor： Tetsuo KIKUCHI ,  Hideki KITAGAWA ,  Hajime IMAI ,  Toshikatsu ITOH ,  Masahiko SUZUKI ,  Teruyuki UEDA ,  Kengo HARA ,  Setsuji NISHIMIYA ,  Tohru DAITOH

IPC: G09G3/36 ,  G02F1/1362 ,  H01L27/32

Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.

公开(公告)号：US20200312885A1

公开(公告)日：2020-10-01

申请号：US16830313

申请日：2020-03-26

Applicant: Sharp Kabushiki Kaisha

Inventor： Hajime IMAI ,  Tohru DAITOH ,  Tetsuo KIKUCHI ,  Masamitsu YAMANAKA ,  Yoshihito HARA ,  Tatsuya KAWASAKI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA

IPC: H01L27/12 ,  H01L29/24 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/465 ,  H01L29/66 ,  G02F1/1368 ,  G02F1/1362 ,  G02F1/1343

Abstract: The oxide semiconductor layer is electrically connected to a source electrode or the source bus line within the source opening formed in the lower insulating layer, each wiring line connection section includes a lower conductive portion formed using the first conductive film, the lower insulating layer extending over the lower conductive portion, an oxide connection layer formed using an oxide film the same as the oxide semiconductor layer and electrically connected to the lower conductive portion within the lower opening formed in the lower insulating layer, an insulating layer covering the oxide connection layer, and an upper conductive portion electrically connected to the oxide connection layer within the upper opening formed in the insulating layer, wherein the oxide connection layer includes a region lower in a specific resistance than the channel region of the oxide semiconductor layer.