公开(公告)号：US20050048741A1

公开(公告)日：2005-03-03

申请号：US10653309

申请日：2003-09-02

申请人： Khoi Phan ,  Bharath Rangarajan ,  Bhanwar Singh

发明人： Khoi Phan ,  Bharath Rangarajan ,  Bhanwar Singh

IPC分类号： G03F7/20 ,  G03F9/00 ,  H01L21/301

CPC分类号： G03F7/70625 ,  G03F7/70633 ,  G03F9/7076 ,  Y10S438/975

摘要： The present invention relates to inspection methods and systems utilized to provide a best means for inspection of a wafer. The methods and systems include wafer-to-reticle alignment, layer-to-layer alignment and wafer surface feature inspection. The wafer-to-reticle alignment is improved by the addition of diagonal lines to existing alignment marks to decrease the intersection size and corresponding area that a desired point can reside. Layer-to-layer alignment is improved in a similar manner by the addition of oblique and/or non-linear line segments to existing overlay targets. Also, providing for wafer surface inspection in a multitude of desired diagonal axes allows for more accurate feature measurement.

摘要翻译： 本发明涉及用于提供用于检查晶片的最佳方法的检查方法和系统。 该方法和系统包括晶片到标线片对准，层间对准和晶片表面特征检查。 通过将对角线添加到现有的对准标记来减小交叉点大小和期望点可以驻留的对应区域来改善晶片到标线阵列对准。 通过向现有覆盖目标添加倾斜和/或非线性线段，以类似的方式改善了层间对齐。 此外，在多个所需的对角轴中提供晶片表面检查允许更精确的特征测量。

公开(公告)号：US06849469B1

公开(公告)日：2005-02-01

申请号：US10677043

申请日：2003-10-01

申请人： Ciby Thomas Thuruthiyil ,  Bhanwar Singh ,  Ramkumar Subramanian

发明人： Ciby Thomas Thuruthiyil ,  Bhanwar Singh ,  Ramkumar Subramanian

IPC分类号： G01N21/47 ,  H01L21/336 ,  H01L21/00

CPC分类号： G01N21/4738 ,  H01L29/665

摘要： Real-time analysis and control of a semiconductor silicidation process. The architecture includes system and methods for monitor and control of a silicidation process during rapid thermal anneal. An FTIR system analyzes selected and/or random regions where silicidation is occurring, and signals the process control system to control the process according to the status of the analyzed silicide formations.

摘要翻译： 实时分析和控制半导体硅化工艺。 该架构包括用于在快速热退火期间监测和控制硅化工艺的系统和方法。 FTIR系统分析在发生硅化的所选择和/或随机区域，并且指示过程控制系统根据分析的硅化物地层的状态来控制过程。

公开(公告)号：US06774365B2

公开(公告)日：2004-08-10

申请号：US09820143

申请日：2001-03-28

申请人： Uzodinma Okoroanyanwu ,  Bhanwar Singh ,  Alden Acheta

发明人： Uzodinma Okoroanyanwu ,  Bhanwar Singh ,  Alden Acheta

IPC分类号： G01N2300

CPC分类号： H01L21/28123

摘要： A process for improving the accuracy of critical dimension measurements of features patterned on a photoresist layer using a scanning electron microscope (SEM) is disclosed herein. The process includes providing an electron beam to the photoresist layer and transforming the surface of the photoresist layer before the SEM inspection. The surface of the photoresist layer is transformed to trap the outgassing volatile species and dissipates built up charge in the photoresist layer, resulting in SEM images without poor image contrast.

摘要翻译： 本文公开了使用扫描电子显微镜（SEM）提高在光致抗蚀剂层上图案化的特征的临界尺寸测量的精度的方法。 该方法包括在SEM检查之前向光致抗蚀剂层提供电子束并转换光致抗蚀剂层的表面。 转变光致抗蚀剂层的表面以捕获除气挥发性物质并在光致抗蚀剂层中消散积聚电荷，导致SEM图像，而图像对比度差。

公开(公告)号：US06746822B1

公开(公告)日：2004-06-08

申请号：US10050484

申请日：2002-01-16

申请人： Bharath Rangarajan ,  Michael K. Templeton ,  Bhanwar Singh

发明人： Bharath Rangarajan ,  Michael K. Templeton ,  Bhanwar Singh

IPC分类号： G03F720

CPC分类号： G03F7/265 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/32139

摘要： Disclosed are methods of processing a semiconductor structure, involving the steps of depositing a light-degradable surface coupling agent on a semiconductor substrate; depositing a resist over the light-degradable surface coupling agent; irradiating portions of the resist, wherein the light-degradable surface coupling agent under the irradiated portions of the resist at least partially decomposes; and developing the resist.

摘要翻译： 公开了处理半导体结构的方法，包括在半导体衬底上沉积可光降解的表面偶联剂的步骤; 在光可降解表面偶联剂上沉积抗蚀剂; 照射抗蚀剂的部分，其中抗蚀剂照射部分下的可光降解表面偶联剂至少部分分解; 并开发抗蚀剂。

公开(公告)号：US06741445B1

公开(公告)日：2004-05-25

申请号：US10050458

申请日：2002-01-16

申请人： Khoi A. Phan ,  Bhanwar Singh ,  Bharath Rangarajan ,  Ramkumar Subramanian

发明人： Khoi A. Phan ,  Bhanwar Singh ,  Bharath Rangarajan ,  Ramkumar Subramanian

IPC分类号： H01T2300

CPC分类号： H01L21/67253

摘要： A system and methodology is provided for monitoring and controlling static charge during wafer and mask fabrication. The static charge on a target device is monitored. If the static charge becomes too high, corrective actions are taken to reduce the static charge. An antistatic solution is dispensed on the target device. The system and methodology provided reduce damage resulting from electrostatic discharge during fabrication. The system and methodology also reduce delays during fabrication by automatically controlling static charge without the need for manual intervention.

摘要翻译： 提供了一种用于在晶片和掩模制造期间监测和控制静电荷的系统和方法。 监视目标设备上的静电荷。 如果静电荷过高，则采取纠正措施减少静电。 抗静电溶液分配在目标装置上。 所提供的系统和方法减少了制造过程中静电放电造成的损坏。 该系统和方法还通过自动控制静电而减少制造过程中的延迟，而无需人工干预。

公开(公告)号：US06724476B1

公开(公告)日：2004-04-20

申请号：US10261756

申请日：2002-10-01

申请人： Khoi A. Phan ,  Bhanwar Singh ,  Bharath Rangarajan

发明人： Khoi A. Phan ,  Bhanwar Singh ,  Bharath Rangarajan

IPC分类号： G01N2100

CPC分类号： G01N21/9501

摘要： One aspect of the present invention relates to a system and method of monitoring for defects on a wafer before and after forming a photoresist layer on the wafer. The system includes a device fabrication system comprising one or more wafer processing system components for producing a device; a defect metrology system integrated within and on track with the fabrication system operative to inspect the wafer for defects before it proceeds to photoresist processing; and a wafer cleaning system for reducing an amount of defects detected on the front and/or back side of the wafer. If the amount of defects have been sufficiently reduced, the front side of the wafer may be coated with a photoresist. Subsequently, the back side of the wafer may be inspected and cleaned while protecting the front side from damage. Cleaning of the wafer may be performed with a thermal shock treatment, for example.

摘要翻译： 本发明的一个方面涉及在晶片上形成光致抗蚀剂层之前和之后对晶片上的缺陷进行监测的系统和方法。 该系统包括装置制造系统，其包括用于产生装置的一个或多个晶片处理系统部件; 在制造系统内部和轨道上集成的缺陷计量系统，其操作用于在进行光致抗蚀剂处理之前检查晶片的缺陷; 以及用于减少在晶片的前侧和/或后侧检测到的缺陷量的晶片清洁系统。 如果缺陷的量已经被充分降低，则晶片的前侧可以涂覆有光致抗蚀剂。 随后，可以在保护前侧免受损伤的同时检查和清洁晶片的背面。 例如，可以进行热冲击处理来进行晶片的清洁。

公开(公告)号：US06702648B1

公开(公告)日：2004-03-09

申请号：US10277559

申请日：2002-10-22

申请人： Steven C. Avanzino ,  Bhanwar Singh ,  Bharath Rangarajan ,  Ramkumar Subramanian

发明人： Steven C. Avanzino ,  Bhanwar Singh ,  Bharath Rangarajan ,  Ramkumar Subramanian

IPC分类号： B24B4900

CPC分类号： B24B37/013 ,  B24B49/12

摘要： One aspect of the present invention relates to a system and method for examining a wafer for delamination in real time while polishing the wafer. The system comprises a polishing system programmed to planarize one or more film layers formed on at least a portion of a semiconductor wafer surface; a real-time metrology system coupled to the polishing system such that the metrology system examines the layers as they are planarized; and one or more delamination sensors, wherein at least a portion of each sensor is integrated into the polishing system in order to provide data to the metrology system and wherein the sensor comprises at least one optical element to detect delamination during polishing. The method involves polishing at least a portion of an uppermost film layer and examining at least a portion of a layer underlying the uppermost film layer for delamination as the uppermost layer is being polished.

摘要翻译： 本发明的一个方面涉及一种用于在抛光晶片的同时检查晶片以实时分层的系统和方法。 该系统包括被编程为平坦化形成在半导体晶片表面的至少一部分上的一个或多个膜层的抛光系统; 耦合到抛光系统的实时计量系统，使得计量系统在平面化时对层进行检查; 和一个或多个分层传感器，其中每个传感器的至少一部分被集成到抛光系统中，以便向计量系统提供数据，并且其中传感器包括至少一个光学元件以在抛光期间检测分层。 该方法包括抛光最上面的薄膜层的至少一部分，并且在最上层被抛光时检查最上面的薄膜层下面的层的至少一部分用于分层。

公开(公告)号：US06684172B1

公开(公告)日：2004-01-27

申请号：US10034165

申请日：2001-12-27

申请人： Ramkumar Subramanian ,  Steven C. Avanzino ,  Christopher F. Lyons ,  Khoi A. Phan ,  Bharath Rangarajan ,  Bhanwar Singh ,  Cyrus E. Tabery

发明人： Ramkumar Subramanian ,  Steven C. Avanzino ,  Christopher F. Lyons ,  Khoi A. Phan ,  Bharath Rangarajan ,  Bhanwar Singh ,  Cyrus E. Tabery

IPC分类号： G01L2500

CPC分类号： C23C16/52 ,  C23C14/547 ,  C23C18/1675 ,  C25D21/12 ,  H01L21/76877

摘要： One aspect of the invention relates to a metal fill process and systems therefor involving providing a standard calibration wafer having a plurality of fill features of known dimensions in a metalization tool; depositing a metal material over the standard calibration wafer; monitoring the deposition of metal material using a sensor system, the sensor system operable to measure one or more fill process parameters and to generate fill process data; controlling the deposition of metal material to minimize void formation using a control system wherein the control system receives fill process data from the sensor system and analyzes the fill process data to generate a feed-forward control data operative to control the metalization tool; and depositing metal material over a production wafer in the metalization tool using the fill process data generated by the sensor system and the control system. The invention further relates to tool characterization processes and systems therefor.

摘要翻译： 本发明的一个方面涉及一种金属填充方法及其系统，其涉及在金属化工具中提供具有已知尺寸的多个填充特征的标准校准晶片; 在标准校准晶片上沉积金属材料; 使用传感器系统监测金属材料的沉积，所述传感器系统可操作以测量一个或多个填充过程参数并产生填充过程数据; 控制金属材料的沉积以最小化使用控制系统的空隙形成，其中控制系统从传感器系统接收填充过程数据并分析填充过程数据以产生可操作以控制金属化工具的前馈控制数据; 以及使用由传感器系统和控制系统产生的填充过程数据在金属化工具中的生产晶片上沉积金属材料。 本发明还涉及其工具表征过程及其系统。

公开(公告)号：US06673524B2

公开(公告)日：2004-01-06

申请号：US09780275

申请日：2001-02-09

申请人： Kouros Ghandehari ,  Bruno LaFontaine ,  Bhanwar Singh

发明人： Kouros Ghandehari ,  Bruno LaFontaine ,  Bhanwar Singh

IPC分类号： C08J718

CPC分类号： G03F1/32 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/24 ,  G03F1/26 ,  G03F1/30 ,  G03F1/68

摘要： An exemplary method of forming an attenuating extreme ultraviolet (EUV) phase-shifting mask is described. This method can include providing a multi-layer mirror over an integrated circuit substrate or a mask blank, providing a buffer layer over the multi-layer mirror, providing a dual element material layer over the buffer layer, and selectively growing features on the integrated circuit substrate or mask blank using a photon assisted chemical vapor deposition (CVD) process when depositing the dual element layer.

摘要翻译： 描述形成衰减极紫外（EUV）移相掩模的示例性方法。 该方法可以包括在集成电路衬底或掩模板上提供多层反射镜，在多层反射镜上提供缓冲层，在缓冲层上提供双重元件材料层，以及在集成电路上选择性地增长特征 衬底或掩模坯料，当沉积双重元件层时，使用光子辅助化学气相沉积（CVD）工艺。

公开(公告)号：US06665065B1

公开(公告)日：2003-12-16

申请号：US09829195

申请日：2001-04-09

申请人： Khoi A. Phan ,  Bhanwar Singh ,  Wolfram Porsche

发明人： Khoi A. Phan ,  Bhanwar Singh ,  Wolfram Porsche

IPC分类号： G01N2100

CPC分类号： G01N21/95692

摘要： A system and method are provided for detecting latent defects in a mask or reticle, which defects may vary as a function of radiation at exposure wavelengths. By way of example, the mask or reticle is inspected, exposed to radiation at a specified wavelength, and then reinspected. A correlation between the inspection results before and after exposure provides an indication of exposure-related defects, which may include defect growth and/or formation of defects caused by the exposure. By way of further illustration, the combination of inspection and exposure of a mask or reticle may be implemented with respect to a pellicized mask or reticle so as to detect additional defects related to use of the pellicle with the mask or reticle.

摘要翻译： 提供了用于检测掩模或掩模版中的潜在缺陷的系统和方法，该缺陷可以随曝光波长的辐射而变化。 作为示例，检查掩模或掩模版，暴露于指定波长的辐射，然后再检查。 暴露前后的检查结果之间的相关性提供暴露相关缺陷的指示，其可以包括由暴露引起的缺陷生长和/或形成缺陷。 为了进一步说明，掩模或掩模版的检查和曝光的组合可以相对于薄膜掩模或掩模版实现，以便检测与使用掩模或掩模版的防护薄膜相关的附加缺陷。