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公开(公告)号：US20110235758A1
公开(公告)日：2011-09-29
申请号：US12790405
申请日：2010-05-28
申请人： Ramin Khoini-Poorfard , Alan F. Hendrickson , Alessandro Piovaccari , David S. Trager , Aslamali A. Rafi , Abdulkerim L. Coban , David Le Goff
发明人： Ramin Khoini-Poorfard , Alan F. Hendrickson , Alessandro Piovaccari , David S. Trager , Aslamali A. Rafi , Abdulkerim L. Coban , David Le Goff
CPC分类号： H04N5/455 , H03G3/001 , H03G3/002 , H03G3/3068 , H04L27/0002 , H04L27/02 , H04L27/08 , H04N5/04 , H04N5/52
摘要： A receiver circuit includes an analog front-end and a digital processing unit. The analog front-end includes an input for receiving a radio frequency (RF) signal, a first control input for receiving a gain adjustment signal, a second control input for receiving a timing signal, and a signal output for providing a digital intermediate frequency (IF) signal. The analog front-end updates gains of a plurality of gain stages according to the gain adjustment signal and in synchronism with the timing signal. The digital processing unit is configured to produce at least one output signal derived from the digital IF signal. The digital processing unit includes a timing recovery circuit configured to generate the timing signal based on the digital IF signal to control timing of the updating gains of each of the plurality of adjustable gain stages.
摘要翻译： 接收机电路包括模拟前端和数字处理单元。 模拟前端包括用于接收射频（RF）信号的输入，用于接收增益调整信号的第一控制输入，用于接收定时信号的第二控制输入和用于提供数字中频的信号输出（ IF）信号。 模拟前端根据增益调整信号更新多个增益级的增益并与定时信号同步。 数字处理单元被配置为产生从数字IF信号导出的至少一个输出信号。 数字处理单元包括定时恢复电路，其被配置为基于数字IF信号生成定时信号，以控制多个可调增益级中的每一个的更新增益的定时。
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公开(公告)号：US20100130153A1
公开(公告)日：2010-05-27
申请号：US12323040
申请日：2008-11-25
IPC分类号： H04B1/16
CPC分类号： H04B1/28 , H03G3/3068
摘要： A receiver (100) includes a first element (110) with a signal input, a control input, a signal output, and gain steps of a first magnitude, a signal processing circuit (120-168) with a signal input coupled to the first element, and a signal output, a second element (180) that has a signal input coupled to signal processing circuit, a control input, a signal output, and gain steps of a second magnitude smaller than the first magnitude, and a controller (180) that has a control output coupled to the first element (110), a control output coupled to the second element (180), and that adjusts receiver (100) gain by changing the first element (110) gain by a first magnitude, changing the second element (180) gain by substantially an inverse first magnitude, and subsequently changing the gain of the second element (180) by steps of the second magnitude to achieve a desired gain.
摘要翻译： 接收器（100）包括具有信号输入的第一元件（110），控制输入，信号输出和第一幅度的增益步长，信号处理电路（120-168），信号输入端与第一 元件和信号输出，具有耦合到信号处理电路的信号输入的第二元件（180），小于第一幅度的第二幅度的控制输入，信号输出和增益步骤，以及控制器（180） ），其具有耦合到所述第一元件（110）的控制输出，耦合到所述第二元件（180）的控制输出，并且通过将所述第一元件（110）增益改变第一大小来调整接收器（100）增益， 第二元件（180）通过基本上相反的第一幅度增益，随后通过第二幅度的步长来改变第二元件（180）的增益，以实现期望的增益。
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公开(公告)号：US20130335639A1
公开(公告)日：2013-12-19
申请号：US13526060
申请日：2012-06-18
申请人： András Vince Horvath , Abdulkerim L. Coban , Pio Balmelli , Ramin Khoini-Poorfard , Alessandro Piovaccari
发明人： András Vince Horvath , Abdulkerim L. Coban , Pio Balmelli , Ramin Khoini-Poorfard , Alessandro Piovaccari
CPC分类号： H04N5/50 , H03J5/24 , H04L25/0292 , H04N5/165 , H04N5/455 , H04N21/42607
摘要： In one embodiment, an internal buffer may be provided within an integrated circuit (IC) to convert a signal to an output current to be output via a pin of the IC, under control of a switch which can be controlled based on a configuration setting of the IC, and may selectively directly couple the signal to the pin when the IC is coupled to an external driver circuit.
摘要翻译： 在一个实施例中，内部缓冲器可以设置在集成电路（IC）内，以在开关的控制下将信号转换成经由IC的引脚输出的输出电流，该开关可以基于配置设置 IC，并且当IC耦合到外部驱动器电路时，可以选择性地将信号耦合到引脚。
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公开(公告)号：US08385867B2
公开(公告)日：2013-02-26
申请号：US12493819
申请日：2009-06-29
申请人： Aslamali A. Rafi , Chunyu Xin , Ruifeng Sun , Abhishek Kammula , Ramin Khoini-Poorfard , Alessandro Piovaccari , Peter J. Vancorenland
发明人： Aslamali A. Rafi , Chunyu Xin , Ruifeng Sun , Abhishek Kammula , Ramin Khoini-Poorfard , Alessandro Piovaccari , Peter J. Vancorenland
IPC分类号： H04B1/18
CPC分类号： H03J3/06 , H03J3/32 , H03J2200/10 , H03J2200/32 , H04N5/50
摘要： In one embodiment, a set of tracking filters to be coupled between an amplifier and a mixer is provided. The tracking filters may be differently configured depending on band of operation. For example, a first set of the filters can be configured to maintain a substantially constant Q value across their operating bandwidth while a second set of the filters can be configured to maintain a substantially constant bandwidth across their operating bandwidth.
摘要翻译： 在一个实施例中，提供要耦合在放大器和混频器之间的一组跟踪滤波器。 根据操作频带，跟踪滤波器可以被不同地配置。 例如，可以将第一组滤波器配置为在其工作带宽上维持基本上恒定的Q值，而第二组滤波器可被配置为在其工作带宽上维持基本恒定的带宽。
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公开(公告)号：US20100328546A1
公开(公告)日：2010-12-30
申请号：US12493819
申请日：2009-06-29
申请人： Aslamali A. Rafi , Chunyu Xin , Ruifeng Sun , Abhishek Kammula , Ramin Khoini-Poorfard , Alessandro Piovaccari , Peter J. Vancorenland
发明人： Aslamali A. Rafi , Chunyu Xin , Ruifeng Sun , Abhishek Kammula , Ramin Khoini-Poorfard , Alessandro Piovaccari , Peter J. Vancorenland
CPC分类号： H03J3/06 , H03J3/32 , H03J2200/10 , H03J2200/32 , H04N5/50
摘要： In one embodiment, a set of tracking filters to be coupled between an amplifier and a mixer is provided. The tracking filters may be differently configured depending on band of operation. For example, a first set of the filters can be configured to maintain a substantially constant Q value across their operating bandwidth while a second set of the filters can be configured to maintain a substantially constant bandwidth across their operating bandwidth.
摘要翻译： 在一个实施例中，提供要耦合在放大器和混频器之间的一组跟踪滤波器。 根据操作频带，跟踪滤波器可以被不同地配置。 例如，可以将第一组滤波器配置为在其工作带宽上维持基本上恒定的Q值，而第二组滤波器可被配置为在其工作带宽上维持基本恒定的带宽。
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公开(公告)号：US08126420B2
公开(公告)日：2012-02-28
申请号：US12005513
申请日：2007-12-27
IPC分类号： H04B1/10
摘要： In one embodiment, the present invention includes a method for digitizing a phase noise value indicative of a level of phase noise present in a LO signal and downconverting an RF signal to a second frequency signal using the LO signal. This downconversion can cause the phase noise to be transferred to the second frequency signal. The method may thus further include removing the phase noise from the second frequency signal using the digitized phase noise value.
摘要翻译： 在一个实施例中，本发明包括一种数字化表示LO信号中存在的相位噪声电平的相位噪声值并使用LO信号将RF信号下变频为第二频率信号的方法。 该下变频可导致相位噪声被传送到第二频率信号。 因此，该方法可以进一步包括使用数字化相位噪声值从第二频率信号中去除相位噪声。
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公开(公告)号：US20090170463A1
公开(公告)日：2009-07-02
申请号：US12005513
申请日：2007-12-27
IPC分类号： H04B1/10
摘要： In one embodiment, the present invention includes a method for digitizing a phase noise value indicative of a level of phase noise present in a LO signal and downconverting an RF signal to a second frequency signal using the LO signal. This downconversion can cause the phase noise to be transferred to the second frequency signal. The method may thus further include removing the phase noise from the second frequency signal using the digitized phase noise value.
摘要翻译： 在一个实施例中，本发明包括一种数字化表示LO信号中存在的相位噪声电平的相位噪声值并使用LO信号将RF信号下变频为第二频率信号的方法。 该下变频可导致相位噪声被传送到第二频率信号。 因此，该方法可以进一步包括使用数字化相位噪声值从第二频率信号中去除相位噪声。
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公开(公告)号：US20130117790A1
公开(公告)日：2013-05-09
申请号：US13344143
申请日：2012-01-05
CPC分类号： H03M3/394 , H03M3/396 , H03M3/398 , H03M3/40 , H03M3/448 , H03M3/45 , H03M3/452 , H03M3/454 , H04N21/6112 , H04N21/6118 , H04N21/6143
摘要： A method of configuring an analog-to-digital converter (ADC) includes configuring the ADC to operate in one of a low-pass filter mode and a band-pass filter mode according to a value of a control signal. In at least one embodiment, the method further includes configuring an integrator gain of the ADC and a feed-forward gain of the ADC based on selection of one of a low-intermediate frequency (LIF) mode and a zero-intermediate frequency (ZIF) mode.
摘要翻译： 配置模数转换器（ADC）的方法包括根据控制信号的值将ADC配置为以低通滤波器模式和带通滤波器模式之一工作。 在至少一个实施例中，该方法还包括基于选择低中频（LIF）模式和零中频（ZIF）之一来配置ADC的积分器增益和ADC的前馈增益， 模式。
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公开(公告)号：US20110065411A1
公开(公告)日：2011-03-17
申请号：US12947285
申请日：2010-11-16
IPC分类号： H04B1/30
CPC分类号： H04B1/16 , H03D7/1441 , H03D7/1458 , H03D7/1483 , H03D2200/0025 , H03D2200/0084 , H03D2200/0086 , H04N5/455
摘要： In one embodiment, the present invention includes a method for receiving a radio frequency (RF) signal and mixing the RF signal with a master clock to obtain a mixed signal, cyclically rotating the mixed signal to each of N gain stages for at least one cycle of the master clock, and summing the outputs of the N gain stages to provide an output signal.
摘要翻译： 在一个实施例中，本发明包括一种用于接收射频（RF）信号并将RF信号与主时钟混合以获得混合信号的方法，将混合信号周期性地旋转至N个增益级中的每一个至少一个周期 并且对N个增益级的输出进行求和以提供输出信号。
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公开(公告)号：US07756504B2
公开(公告)日：2010-07-13
申请号：US11824417
申请日：2007-06-29
IPC分类号： H04B1/26
CPC分类号： H03D7/00 , H03D7/1441 , H03D7/1458 , H03D7/1483 , H03D7/165 , H03D2200/0084 , H03D2200/0086
摘要： In one embodiment, the present invention includes a mixer circuit to receive and generate a mixed signal from a radio frequency (RF) signal and a master clock signal, a switch stage coupled to an output of the mixer circuit to rotatingly switch the mixed signal to multiple gain stages coupled to the switch stage, and a combiner to combine an output of the gain stages.
摘要翻译： 在一个实施例中，本发明包括一个混频器电路，用于接收和产生来自射频（RF）信号和主时钟信号的混合信号，耦合到混频器电路的输出的开关级，以将混合信号旋转切换到 耦合到开关级的多个增益级，以及组合器，以组合增益级的输出。
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