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42 条记录 (耗时 0.036 秒)

    Generic packet filtering
    21.
    发明授权
    Generic packet filtering 有权
    通用包过滤

    公开(公告)号：US08873367B2

    公开(公告)日：2014-10-28

    申请号：US13411146

    申请日：2012-03-02

    申请人： Michelle Perras ,  Juan Carlos Zuniga ,  Alexander Reznik ,  Reeteshkumar Varshney ,  Imran Khan

    发明人： Michelle Perras ,  Juan Carlos Zuniga ,  Alexander Reznik ,  Reeteshkumar Varshney ,  Imran Khan

    IPC分类号： H04W4/00 ,  H04L29/06 ,  H04W28/06

    CPC分类号： H04L69/22 ,  H04L69/14 ,  H04W28/06

    摘要： Embodiments contemplate one or more techniques for packet filtering. One or more embodiments may apply specific routing and/or forwarding rules on some or each packet when a device has one or more, or multiple, interfaces. Contemplated filtering techniques may be implemented in a module and/or without modifying an IP stack. The contemplated packet filtering techniques may apply to a terminal in uplink and/or downlink as well as to any network node. An incoming packet table may be created using 5-tuple, 6-tuple, and/or tags, among other mechanisms, to support incoming and/or outgoing packet filtering.

    摘要翻译： 实施例考虑了一种或多种用于分组过滤的技术。 一个或多个实施例可以在设备具有一个或多个或多个接口时在一些或每个分组上应用特定路由和/或转发规则。 考虑过滤技术可以在模块中实现和/或不修改IP堆栈。 预期的分组过滤技术可以应用于上行链路和/或下行链路中的终端以及任何网络节点。 可以使用5元组，6元组和/或标签以及其他机制来创建输入分组表，以支持传入和/或传出分组过滤。

    Low noise JFET
    23.
    发明授权
    Low noise JFET 有权
    低噪声JFET

    公开(公告)号：US08110857B2

    公开(公告)日：2012-02-07

    申请号：US12713866

    申请日：2010-02-26

    申请人： Pinghai Hao ,  Imran Khan ,  Joe Trogolo

    发明人： Pinghai Hao ,  Imran Khan ,  Joe Trogolo

    IPC分类号： H01L29/66

    CPC分类号： H01L29/8086 ,  H01L29/66901 ,  H01L29/808

    摘要： A low noise (1/f) junction field effect transistor (JFET) is disclosed, wherein multiple implants push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise.

    摘要翻译： 公开了一种低噪声（1 / f）结场效应晶体管（JFET），其中多个种植体推动晶体管的导电路径离开形成晶体管的层的表面。 以这种方式，导电路径中的电流不太可能受到可能存在于层的表面处的缺陷的干扰，从而减轻（1 / f）噪声。

    Method and apparatus for performing semiconductor memory operations
    24.
    发明授权
    Method and apparatus for performing semiconductor memory operations 有权
    用于执行半导体存储器操作的方法和装置

    公开(公告)号：US08040738B2

    公开(公告)日：2011-10-18

    申请号：US12346699

    申请日：2008-12-30

    申请人： Hagop Nazarian ,  Imran Khan ,  Chieu-Yin Chia

    发明人： Hagop Nazarian ,  Imran Khan ,  Chieu-Yin Chia

    IPC分类号： G11C11/34

    CPC分类号： G11C16/24 ,  G11C16/26 ,  G11C16/3454

    摘要： A semiconductor memory device and a method for performing a memory operation in the semiconductor memory device are provided. The semiconductor memory device includes a plurality of predetermined memory arrays, a bitline decoder, and a controller. The controller provides the memory operation signal to the bitline decoder and, after precharging bitlines of the plurality of predetermined memory arrays, performs the memory operation on selected memory cells in the one or more of the plurality of predetermined memory arrays in accordance with the memory operation signal. The bitline decoder includes a plurality of sector select transistors and determines selected ones of the plurality of predetermined memory arrays and selected rows and unselected rows within the selected ones of the plurality of predetermined memory arrays in response to the memory operation signal. The bitline decoder also precharges the bitlines of the plurality of predetermined memory arrays to a first voltage potential then shuts off the sector select transistors of unselected ones of the plurality of predetermined memory arrays and the unselected rows of the selected ones of the plurality of predetermined memory arrays while maintaining the sector select transistors of the selected rows of the selected ones of the plurality of predetermined memory arrays at the first voltage potential prior to the controller performing the memory operation.

    摘要翻译： 提供半导体存储器件和用于在半导体存储器件中执行存储器操作的方法。 半导体存储器件包括多个预定存储器阵列，位线解码器和控制器。 控制器向位线解码器提供存储器操作信号，并且在预充电多个预定存储器阵列的位线之后，根据存储器操作对多个预定存储器阵列中的一个或多个存储器单元中的选定存储单元执行存储器操作 信号。 位线解码器包括多个扇区选择晶体管，并且响应于存储器操作信号确定多个预定存储器阵列中的选定的行以及多个预定存储器阵列中的选定行中的选定行和未选择的行。 位线解码器还将多个预定存储器阵列的位线预先充电到第一电压电位，然后关闭多个预定存储器阵列中未选择的存储器阵列的扇区选择晶体管和多个预定存储器中的所选择的存储器的未选择的行 阵列，同时在所述控制器执行所述存储器操作之前，将所述多个预定存储器阵列中的选定行的选定行的扇区选择晶体管保持在所述第一电压电位。

    Low cost fabrication method for high voltage, high drain current MOS transistor
    25.
    发明授权
    Low cost fabrication method for high voltage, high drain current MOS transistor 有权
    低成本高漏极电流MOS晶体管制造方法

    公开(公告)号：US06930005B2

    公开(公告)日：2005-08-16

    申请号：US10725642

    申请日：2003-12-02

    申请人： Taylor R. Efland ,  Jozef C. Mitros ,  Imran Khan

    发明人： Taylor R. Efland ,  Jozef C. Mitros ,  Imran Khan

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

    CPC分类号： H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

    摘要： A method for reducing the drain resistance of a drain-extended MOS transistor in a semiconductor wafer, while maintaining a high transistor breakdown voltage. The method provides a first well (502) of a first conductivity type, operable as the extension of the transistor drain (501) of the first conductivity type; portions of the well are covered by a first insulator (503) having a first thickness. A second well (504) of the opposite conductivity type is intended to contain the transistor source (506) of the first conductivity type; portions of the second well are covered by a second insulator (507) thinner than the first insulator. The first and second wells form a junction (505) that terminates at the second insulator (530a, 530b). The method deposits a photoresist layer (510) over the wafer, which is patterned by opening a window (510a) that extends from the drain to the junction termination. Next, ions (540) of the first conductivity type are implanted through the window into the first well; these said ions have an energy to limit the penetration depth (541) to the first insulator thickness, and a dose to create a well region (560) of high doping concentration adjacent to the junction termination (530a).

    摘要翻译： 一种在保持高晶体管击穿电压的同时降低半导体晶片中的漏极扩展MOS晶体管的漏极电阻的方法。 该方法提供第一导电类型的第一阱（50​​2），其可操作为第一导电类型的晶体管漏极（501）的延伸; 阱的一部分被具有第一厚度的第一绝缘体（503）覆盖。 相反导电类型的第二阱（504）旨在包含第一导电类型的晶体管源（506）; 第二阱的部分被比第一绝缘体薄的第二绝缘体（507）覆盖。 第一和第二阱形成终止于第二绝缘体（530a，530b）的结（505）。 该方法将光致抗蚀剂层（510）沉积在晶片之上，其通过打开从漏极延伸到结终端的窗口（510a）而被图案化。 接下来，通过窗口将第一导电类型的离子（540）注入到第一阱中; 这些所述离子具有将穿透深度（541）限制到第一绝缘体厚度的能量，以及用于产生邻近连接终端（530a）的高掺杂浓度的阱区（560）的剂量。

    MOS transistors having higher drain current without reduced breakdown voltage
    26.
    发明授权
    MOS transistors having higher drain current without reduced breakdown voltage 有权
    MOS晶体管具有较高的漏极电流，而不降低击穿电压

    公开(公告)号：US06873021B1

    公开(公告)日：2005-03-29

    申请号：US10725641

    申请日：2003-12-02

    申请人： Jozef C. Mitros ,  Imran Khan ,  Taylor R. Efland

    发明人： Jozef C. Mitros ,  Imran Khan ,  Taylor R. Efland

    IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/76 ,  H01L29/78

    CPC分类号： H01L29/7816 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66681

    摘要： A drain-extended MOS transistor in a semiconductor wafer (300) of a first conductivity type comprises a first well (315) of the first conductivity type, operable as the extension of the transistor drain (305) of the first conductivity type, and covered by a first insulator (312) having a first thickness, and further a second well (302) of the opposite conductivity type, intended to contain the transistor source (304) of the first conductivity type, and covered by a second insulator (311) thinner than said first insulator (312). First and second wells form a junction (330) that terminates (320, 321) at the second insulator. The first well has a region (360) in the proximity of the junction termination, which has a higher doping concentration than the remainder of the first well and extends not deeper than the first insulator thickness. Region (360) of higher doping concentration reduces the transistor drain resistance so that the drain current is increased to approximately twice the value it had without the higher doping concentration, while the transistor breakdown voltage remains determined by the (low) doping concentration of the remainder of first well (315).

    摘要翻译： 第一导电类型的半导体晶片（300）中的漏极扩展MOS晶体管包括第一导电类型的第一阱（315），可用作第一导电类型的晶体管漏极（305）的延伸部分，并且被覆盖 通过具有第一厚度的第一绝缘体（312）和另外具有相反导电类型的第二阱（302），用于容纳第一导电类型的晶体管源（304），并被第二绝缘体（311）覆盖， 比所述第一绝缘体（312）薄。 第一和第二阱形成在第二绝缘体处终止（320,321）的结（330）。 第一阱具有在接合端子附近的区域（360），其具有比第一阱的其余部分更高的掺杂浓度，并且延伸不比第一绝缘体厚度更深。 掺杂浓度较高的区域（360）降低了晶体管漏极电阻，使得漏极电流增加到其没有较高掺杂浓度的值的两倍，而晶体管击穿电压保持由其余部分的（低）掺杂浓度确定 的第一井（315）。

    Zero temperature coefficient capacitor
    29.
    发明授权
    Zero temperature coefficient capacitor 有权
    零温度系数电容

    公开(公告)号：US08373215B2

    公开(公告)日：2013-02-12

    申请号：US13267674

    申请日：2011-10-06

    申请人： Weidong Tian ,  Imran Khan

    发明人： Weidong Tian ,  Imran Khan

    IPC分类号： H01L29/92

    CPC分类号： H01L28/40 ,  H01L27/0629 ,  H01L29/94

    摘要： A zero temperature coefficient (ZTC) capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7×1020 atoms/cm3 and 2.3×1020 atoms/cm3. An integrated circuit containing a ZTC capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7×1020 atoms/cm3 and 2.3×1020 atoms/cm3. A process of forming an integrated circuit containing a ZTC capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7×1020 atoms/cm3 and 2.3×1020 atoms/cm3.

    摘要翻译： 零温度系数（ZTC）电容器，其包括磷密度在1.7×1020原子/ cm3至2.3×1020原子/ cm3之间的二氧化硅介电层。 一种包含ZTC电容器的集成电路，其包括磷密度为1.7×1020原子/ cm3至2.3×1020原子/ cm3的二氧化硅电介质层。 形成包含Zinc电容器的集成电路的过程，该电容器包括磷密度为1.7×1020原子/ cm3至2.3×1020原子/ cm3的二氧化硅介电层。