Semiconductor device manufacture method
    21.
    发明申请
    Semiconductor device manufacture method 有权
    半导体器件制造方法

    公开(公告)号:US20050159005A1

    公开(公告)日:2005-07-21

    申请号:US10838218

    申请日:2004-05-05

    摘要: An electric conductive film is formed on the insulating surface of a substrate, the substrate having a trench formed on the insulating surface, and the conductive film being filled in the trench. Chemical mechanical polishing is executed to expose the insulating surface of the substrate and leave a portion of the conductive film in the trench. The surface of the substrate having the exposed conductive film in the trench and the exposed insulating surface is exposed to first liquid. After being exposed to the first liquid, the surface of the substrate is exposed to second liquid. The first liquid is either solution which contains at least one first substance selected from a first group consisting of benzotriazole, derivative of benzotriazole and interfacial active agent, or water. The second solution is solution which contains the first substance at a density higher than a density of the first liquid.

    摘要翻译: 在基板的绝缘表面上形成导电膜,该基板在绝缘表面上形成沟槽,并且导电膜填充在沟槽中。 执行化学机械抛光以暴露基板的绝缘表面并将导电膜的一部分留在沟槽中。 在沟槽中具有暴露的导电膜的衬底的表面和暴露的绝缘表面暴露于第一液体。 在暴露于第一液体之后,将基板的表面暴露于第二液体。 第一液体是含有选自苯并三唑,苯并三唑衍生物和界面活性剂的第一组中的至少一种第一物质或水的溶液。 第二种溶液是含有比第一种液体密度高的第一物质的溶液。

    Designing and fabrication of a semiconductor device
    22.
    发明授权
    Designing and fabrication of a semiconductor device 有权
    设计和制造半导体器件

    公开(公告)号:US07424688B2

    公开(公告)日:2008-09-09

    申请号:US11333212

    申请日:2006-01-18

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5068 H01L21/31053

    摘要: Designing method of an electronic device subjected to a chemical mechanical polishing process in a fabrication process thereof is conducted according to the steps of: dividing a substrate surface into first sub-regions; optimizing a coverage ratio of hard-to-polish regions in the first sub-regions to fall in a first predetermined range corresponding to the first sub-regions; dividing the substrate surface into second sub-regions different from the first sub-regions; and optimizing a coverage ratio of the hard-to-polish regions in the second sub-regions to fall in a second predetermined range corresponding to the second sub-regions, wherein patterns having a shorter edge of 5 μm or less are excluded from the optimization.

    摘要翻译: 根据以下步骤进行在其制造工艺中进行化学机械抛光工艺的电子器件的设计方法:将衬底表面分成第一子区; 优化所述第一子区域中的硬抛光区域的覆盖率落在对应于所述第一子区域的第一预定范围内; 将基板表面分成与第一子区域不同的第二子区域; 并且优化所述第二子区域中的所述硬抛光区域的覆盖率落入对应于所述第二子区域的第二预定范围中,其中具有5μm或更小边缘的边缘的图案被从所述优化中排除 。

    Designing and fabrication of a semiconductor device
    25.
    发明申请
    Designing and fabrication of a semiconductor device 有权
    设计和制造半导体器件

    公开(公告)号:US20050160381A1

    公开(公告)日:2005-07-21

    申请号:US10849368

    申请日:2004-05-20

    CPC分类号: G06F17/5068 H01L21/31053

    摘要: Designing method of an electronic device subjected to a chemical mechanical polishing process in a fabrication process thereof is conducted according to the steps of: dividing a substrate surface into first sub-regions; optimizing a coverage ratio of hard-to-polish regions in the first sub-regions to fall in a first predetermined range corresponding to the first sub-regions; dividing the substrate surface into second sub-regions different from the first sub-regions; and optimizing a coverage ratio of the hard-to-polish regions in the second sub-regions to fall in a second predetermined range corresponding to the second sub-regions, wherein patterns having a shorter edge of 5 μm or less are excluded from the optimization.

    摘要翻译: 根据以下步骤进行在其制造工艺中进行化学机械抛光工艺的电子器件的设计方法:将衬底表面分成第一子区; 优化所述第一子区域中的硬抛光区域的覆盖率落在对应于所述第一子区域的第一预定范围内; 将基板表面分成与第一子区域不同的第二子区域; 并且优化所述第二子区域中的所述硬抛光区域的覆盖率落入对应于所述第二子区域的第二预定范围中,其中具有5μm或更小边缘的边缘的图案被从所述优化中排除 。

    Semiconductor device manufacture method preventing dishing and erosion during chemical mechanical polishing
    26.
    发明授权
    Semiconductor device manufacture method preventing dishing and erosion during chemical mechanical polishing 有权
    半导体器件制造方法,防止化学机械抛光过程中的凹陷和侵蚀

    公开(公告)号:US06686285B2

    公开(公告)日:2004-02-03

    申请号:US10326378

    申请日:2002-12-23

    IPC分类号: H01L21311

    摘要: A first insulating film is formed on an underlying substrate, the first insulating film being made of a first insulating material. A second insulating film is formed on the first insulating film, the second insulating film being made of a second insulating material different from the first insulating material. A trench is formed through the second and first insulating film, the trench reaching at least an intermediate depth of the first insulating film. A wiring layer made of a conductive material is deposited on the second insulating film, the wiring layer burying the trench. The wiring layer is polished to leave the wiring layer in the trench. The wiring layer and second insulating film are polished until the first insulating film is exposed. Irregularity such as dishing and erosion can be suppressed from being formed.

    摘要翻译: 第一绝缘膜形成在下面的基底上,第一绝缘膜由第一绝缘材料制成。 在第一绝缘膜上形成第二绝缘膜,第二绝缘膜由与第一绝缘材料不同的第二绝缘材料制成。 通过第二和第一绝缘膜形成沟槽,沟槽到达第一绝缘膜的至少中间深度。 在第二绝缘膜上沉积由导电材料制成的布线层,布线层埋入沟槽。 对布线层进行抛光以将沟槽中的布线层留下。 布线层和第二绝缘膜被抛光直到第一绝缘膜露出。 可以抑制凹陷和侵蚀等不规则形成。

    SEMICONDUCTOR DEVICE FABRICATING METHOD, AND SEMICONDUCTOR FABRICATING DEVICE
    27.
    发明申请
    SEMICONDUCTOR DEVICE FABRICATING METHOD, AND SEMICONDUCTOR FABRICATING DEVICE 审中-公开
    半导体器件制造方法和半导体制造装置

    公开(公告)号:US20100035523A1

    公开(公告)日:2010-02-11

    申请号:US12505639

    申请日:2009-07-20

    IPC分类号: B24B1/00 B24B7/20 B24B9/06

    CPC分类号: B24B37/32

    摘要: A method for fabricating a semiconductor device includes: supporting a semiconductor substrate formed with a polishing target film by a polishing head; and polishing the polishing target film while restricting movement in a radial direction of the semiconductor substrate by a retainer formed on the polishing head with a tilted surface formed on an inner peripheral section of the retainer, wherein when the polishing target film is polished, an outer peripheral surface of the semiconductor substrate comes into contact with the tilted surface formed on the inner peripheral section of the retainer.

    摘要翻译: 一种制造半导体器件的方法包括:通过抛光头支撑形成有抛光目标膜的半导体衬底; 并且通过形成在所述研磨头上的保持器在所述保持器的内周部形成有倾斜面的同时限制半导体衬底的径向的移动来研磨抛光对象膜,其中,当抛光对象膜被抛光时, 半导体基板的周面与形成在保持器的内周部的倾斜面接触。

    Semiconductor device manufacture method
    28.
    发明授权
    Semiconductor device manufacture method 有权
    半导体器件制造方法

    公开(公告)号:US07338905B2

    公开(公告)日:2008-03-04

    申请号:US10838218

    申请日:2004-05-05

    IPC分类号: H01L21/302 H01L21/461

    摘要: An electric conductive film is formed on the insulating surface of a substrate, the substrate having a trench formed on the insulating surface, and the conductive film being filled in the trench. Chemical mechanical polishing is executed to expose the insulating surface of the substrate and leave a portion of the conductive film in the trench. The surface of the substrate having the exposed conductive film in the trench and the exposed insulating surface is exposed to first liquid. After being exposed to the first liquid, the surface of the substrate is exposed to second liquid. The first liquid is either solution which contains at least one first substance selected from a first group consisting of benzotriazole, derivative of benzotriazole and interfacial active agent, or water. The second solution is solution which contains the first substance at a density higher than a density of the first liquid.

    摘要翻译: 在基板的绝缘表面上形成导电膜,该基板在绝缘表面上形成沟槽,并且导电膜填充在沟槽中。 执行化学机械抛光以暴露基板的绝缘表面并将导电膜的一部分留在沟槽中。 在沟槽中具有暴露的导电膜的衬底的表面和暴露的绝缘表面暴露于第一液体。 在暴露于第一液体之后,将基板的表面暴露于第二液体。 第一液体是含有选自苯并三唑,苯并三唑衍生物和界面活性剂的第一组中的至少一种第一物质或水的溶液。 第二种溶液是含有比第一种液体密度高的第一物质的溶液。

    Multi-layer wiring structure with dummy patterns for improving surface flatness
    29.
    发明授权
    Multi-layer wiring structure with dummy patterns for improving surface flatness 有权
    具有用于提高表面平坦度的虚拟图案的多层布线结构

    公开(公告)号:US07161248B2

    公开(公告)日:2007-01-09

    申请号:US10898167

    申请日:2004-07-26

    IPC分类号: H01L23/48

    摘要: A first area, a ring shape second area surrounding the first area, and a third area surrounding the second area are defined on the surface of a support substrate. A first wiring layer is disposed above the support substrate. A wiring is formed in the third area, dummy patterns being formed in the second area, and conductive patterns are not formed in the first area. A functional element is disposed above the first wiring layer and in the first area.

    摘要翻译: 在支撑基板的表面上限定第一区域,围绕第一区域的环形第二区域和围绕第二区域的第三区域。 第一布线层设置在支撑基板的上方。 在第三区域中形成布线,在第二区域中形成虚设图案,并且在第一区域中不形成导电图案。 功能元件设置在第一布线层上方和第一区域中。

    Designing a semiconductor device layout using polishing regions
    30.
    发明授权
    Designing a semiconductor device layout using polishing regions 有权
    使用抛光区域设计半导体器件布局

    公开(公告)号:US07017133B2

    公开(公告)日:2006-03-21

    申请号:US10849368

    申请日:2004-05-20

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5068 H01L21/31053

    摘要: Designing method of an electronic device subjected to a chemical mechanical polishing process in a fabrication process thereof is conducted according to the steps of: dividing a substrate surface into first sub-regions; optimizing a coverage ratio of hard-to-polish regions in the first sub-regions to fall in a first predetermined range corresponding to the first sub-regions; dividing the substrate surface into second sub-regions different from the first sub-regions; and optimizing a coverage ratio of the hard-to-polish regions in the second sub-regions to fall in a second predetermined range corresponding to the second sub-regions, wherein patterns having a shorter edge of 5 μm or less are excluded from the optimization.

    摘要翻译: 根据以下步骤进行在其制造工艺中进行化学机械抛光工艺的电子器件的设计方法:将衬底表面分成第一子区; 优化所述第一子区域中的硬抛光区域的覆盖率落在对应于所述第一子区域的第一预定范围内; 将基板表面分成与第一子区域不同的第二子区域; 并且优化所述第二子区域中的所述硬抛光区域的覆盖率落入对应于所述第二子区域的第二预定范围中,其中具有5μm或更小边缘的边缘的图案被从所述优化中排除 。