公开(公告)号：US5210847A

公开(公告)日：1993-05-11

申请号：US354513

申请日：1989-05-19

申请人： Gary W. Thome ,  James H. Nuckols ,  Paul R. Culley ,  Gary L. Brasher

发明人： Gary W. Thome ,  James H. Nuckols ,  Paul R. Culley ,  Gary L. Brasher

IPC分类号： G06F12/08 ,  G06F12/12 ,  G06F15/16

CPC分类号： G06F12/0888

摘要： A computer system uses a random access memory to store memory characteristic information, such as noncacheable status. The memory is coupled to the processor address lines to produce an output representative of the memory address block, the output used as appropriate, for example by the noncacheable address input of a cache controller. Latches are used to store programming mode, write or read operation and data values. The reading and writing of the random access memory is performed without disturbing the main memory.

公开(公告)号：US5165037A

公开(公告)日：1992-11-17

申请号：US378580

申请日：1989-07-10

申请人： Paul R. Culley

发明人： Paul R. Culley

IPC分类号： G06F13/40 ,  G06F13/42

CPC分类号： G06F13/4243 ,  G06F13/4018

摘要： A computer system which utilizes two different sets of address control and state information signals for transferring information of the same or different widths is disclosed. The use of two sets of signals allows master units to utilize only one set and a system board determines when the second set of signals must be used to complete the transfer and controls the second set of signals as necessary. The system board provides the necessary information routing and latching to properly transfer the information.

摘要翻译： 公开了一种利用两组不同地址控制和状态信息信号传送相同或不同宽度的信息的计算机系统。 使用两组信号允许主机单元仅使用一组，并且系统板确定何时必须使用第二组信号来完成传输，并根据需要控制第二组信号。 系统板提供必要的信息路由和锁存，以正确传输信息。

公开(公告)号：US5027313A

公开(公告)日：1991-06-25

申请号：US236620

申请日：1988-08-25

申请人： Paul R. Culley

发明人： Paul R. Culley

IPC分类号： G06F12/06

CPC分类号： G06F12/0684

摘要： An apparatus for determining maximum usable memory size is disclosed. Permanent connections on a base memory unit and additional memory modules provide signals indicative of the amount of memory installed at each location. The signals are read by the processor and used in conjunction with a lookup table or size counting method to determine maximum usable memory size and the existence of installation or operation errors. The maximum size is written to a latch which provides the value to logic which enables the appropriate memory locations when addressed by the processor.

摘要翻译： 公开了一种用于确定最大可用存储器大小的装置。 基本存储器单元和附加存储器模块上的永久连接提供指示在每个位置安装的存储器的量的信号。 信号由处理器读取并与查找表或大小计数方法一起使用以确定最大可用存储器大小以及安装或操作错误的存在。 最大大小被写入锁存器，该锁存器将逻辑值提供给处理器寻址时允许适当的存储单元。

公开(公告)号：US07783876B2

公开(公告)日：2010-08-24

申请号：US11742594

申请日：2007-05-01

申请人： Paul R. Culley ,  Kevin B. Leigh

发明人： Paul R. Culley ,  Kevin B. Leigh

IPC分类号： G06F15/177

CPC分类号： G06F1/26 ,  G06F1/189

摘要： A system that comprises a first electronic device comprising a non-volatile memory. The system also comprises another electronic device in communication with the first electronic device and comprising a second non-volatile memory. The system further comprises a control logic coupled to the first and second electronic devices. Each of the non-volatile memories stores electrical characteristics associated with a corresponding electronic device. Prior to booting up the first or second electronic device, the control logic obtains and compares at least some of the electrical characteristics and disables the communication as a result of the comparison.

摘要翻译： 一种包括包括非易失性存储器的第一电子设备的系统。 该系统还包括与第一电子设备通信并且包括第二非易失性存储器的另一电子设备。 该系统还包括耦合到第一和第二电子设备的控制逻辑。 每个非易失性存储器存储与相应的电子设备相关联的电特性。 在引导第一或第二电子设备之前，控制逻辑获得并比较至少一些电气特性，并且作为比较的结果来禁止通信。

公开(公告)号：US5872941A

公开(公告)日：1999-02-16

申请号：US659141

申请日：1996-06-05

申请人： Alan L. Goodrum ,  John M. MacLaren ,  Christopher J. Pettey ,  Paul R. Culley

发明人： Alan L. Goodrum ,  John M. MacLaren ,  Christopher J. Pettey ,  Paul R. Culley

IPC分类号： G06F13/36 ,  G06F13/362 ,  G06F13/364 ,  G06F13/40 ,  G06F13/00 ,  G06F13/16

CPC分类号： G06F13/364 ,  G06F13/4054

摘要： A computer system includes a data storage device on a first data bus, a requesting device that initiates a delayed request on a second data bus, and a bridge device that delivers the delayed request to the first data bus and, after the requesting device regains control of the second data bus, begins providing data to the requesting device while the data storage device is providing the requested data to the bridge device.

摘要翻译： 计算机系统包括在第一数据总线上的数据存储设备，在第二数据总线上启动延迟请求的请求设备，以及将延迟的请求传送到第一数据总线的桥接设备，并且在请求设备重新获得控制之后 的第二数据总线开始向数据存储设备提供所请求的数据到桥接设备时向请求设备提供数据。

公开(公告)号：US5611078A

公开(公告)日：1997-03-11

申请号：US480874

申请日：1995-06-07

申请人： David A. Miller ,  Kenneth A. Jansen ,  Paul R. Culley ,  Mark Taylor ,  Javier F. Izquierdo

发明人： David A. Miller ,  Kenneth A. Jansen ,  Paul R. Culley ,  Mark Taylor ,  Javier F. Izquierdo

IPC分类号： G06F1/24 ,  G06F12/08 ,  G06F15/177 ,  G06F13/00

CPC分类号： G06F12/0802 ,  G06F1/24 ,  G06F15/177

摘要： A method and system for independently resetting primary and secondary processors 20 and 120 respectively under program control in a multiprocessor, cache memory system. Processors 20 and 120 are reset without causing cache memory controllers 24 and 124 to reset.

摘要翻译： 一种用于在多处理器，高速缓冲存储器系统中的程序控制下分别独立地重置主处理器20和第二处理器120的方法和系统。 复位处理器20和120而不使高速缓冲存储器控制器24和124复位。

公开(公告)号：US5553310A

公开(公告)日：1996-09-03

申请号：US955930

申请日：1992-10-02

申请人： Mark Taylor ,  Paul R. Culley ,  Maria L. Melo ,  Roger E. Tipley

发明人： Mark Taylor ,  Paul R. Culley ,  Maria L. Melo ,  Roger E. Tipley

IPC分类号： G06F13/364 ,  G06F13/14 ,  G06F13/18

CPC分类号： G06F13/364

摘要： Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2).times.(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allows a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

摘要翻译： 用于确定几个CPU中的哪一个接收优先级以在多处理器系统中成为主机总线的总线主机的三个优先级方案，以及用于将控制从一个总线主机传送到另一个总线主机的仲裁方案。 每个优先排序方案优先考虑n个元素，其中总共（n / 2）x（n-1）个优先级位监视每对元素之间的相对优先级。 当与该元素相关联的n-1个优先级位中的每一个指向它时，元素接收最高优先级。 在仲裁方案中，主机总线的当前总线主机确定主机总线的控制传输何时由优先级排列方案之一决定。 仲裁方案给予EISA总线主机，RAM刷新和DMA优先于作为总线主机的CPU，并允许临时总线主机中断当前总线主机以执行回写高速缓存干预周期。 仲裁方案还支持在尝试锁定循环时中止CPU的地址流水线，突发，拆分事务和预留。 地址流水线允许下一个总线主机在下一个总线主机的数据传输阶段开始之前断言其地址和状态信号。 分割事务允许CPU向EISA总线发布读取，以将主机总线仲裁到另一个设备，而不需要重新仲裁主机总线来检索数据。 即使主机总线被另一个设备控制，数据在空闲时也在主机总线上被断言。

公开(公告)号：US5463761A

公开(公告)日：1995-10-31

申请号：US955500

申请日：1992-10-02

申请人： Paul R. Culley

发明人： Paul R. Culley

IPC分类号： G06F1/14 ,  G06F1/00

CPC分类号： G06F1/14

摘要： A computer system provides a 48-bit timer having 120 ns resolution and possessing a rollover period in excess of one year. The preferred embodiment includes two system data buffers (SDBs), each of which includes a full 48-bit timer. The timers are synchronized, and the output of each timer is provided to the host bus in alternating pairs of bits, so that half of the data bits are provided by the first SDB and half of the timer bits are provided by the second SDB. The timer may be read either as a 48-bit timer or a 32-bit timer.

摘要翻译： 计算机系统提供了一个具有120ns分辨率并具有超过一年的翻转周期的48位定时器。 优选实施例包括两个系统数据缓冲器（SDB），每个系统数据缓冲器包括一个完整的48位定时器。 定时器被同步，并且每个定时器的输出以交替的位对提供给主机总线，使得一半的数据位由第一SDB提供，一半的定时器位由第二SDB提供。 定时器可以被读取为48位定时器或32位定时器。

公开(公告)号：US5406590A

公开(公告)日：1995-04-11

申请号：US965189

申请日：1992-10-23

申请人： Joseph P. Miller ,  Paul R. Culley

发明人： Joseph P. Miller ,  Paul R. Culley

IPC分类号： H03L7/089 ,  H03L7/095 ,  H03L7/18 ,  H03D3/24

CPC分类号： H03L7/18 ,  H03L7/0891 ,  H03L7/095

摘要： A method of starting up a system clock that has been generated by a phase-locked loop and correcting edge placement errors during coasting periods of the phase locked loop, and circuitry for accomplishing those methods. A low frequency master clock signal is distributed to circuits that generate high frequency local clock signals. These circuits generate the high frequency local clock signals using phase-locked loops in a frequency multiplier configuration. Lock indicator circuitry determines when the phase-locked loop has locked onto the master clock signal and then enables output buffers that then provide the high frequency clock signals to components in the system which need those local clocks. An intermediate frequency signal is fed back to the input of the voltage controlled oscillator in the phase locked loop to correct edge placement errors. A slightly earlier or leading version of the signal is used to correct cycle length variations without inducing duty cycle variations.

摘要翻译： 一种启动由锁相环生成的系统时钟的方法，并且在锁相环的惯性周期期间校正边缘放置误差，以及用于完成这些方法的电路。 低频主时钟信号被分配到产生高频本地时钟信号的电路。 这些电路使用倍频器配置中的锁相环产生高频本地时钟信号。 锁定指示器电路确定锁相环何时锁定在主时钟信号上，然后启用输出缓冲器，然后将高频时钟信号提供给需要这些本地时钟的系统中的组件。 将中频信号反馈到锁相环中的压控振荡器的输入端，以校正边缘放置误差。 信号的稍早一些或者是领先的版本被用于校正周期长度变化，而不会引起占空比变化。

公开(公告)号：US5392436A

公开(公告)日：1995-02-21

申请号：US249665

申请日：1994-05-26

申请人： Kenneth A. Jansen ,  Montgomery C. McGraw ,  David A. Miller ,  Paul R. Culley

发明人： Kenneth A. Jansen ,  Montgomery C. McGraw ,  David A. Miller ,  Paul R. Culley

IPC分类号： G06F13/362 ,  G06F13/36 ,  G06F13/18

CPC分类号： G06F13/362

摘要： A method and apparatus for arbitrating between multiple processors that can be incorporated into an arbitration scheme that is designed to include only a single processor. The method includes consolidating the individual bus requests of each processor into a single bus request supplied to the single processor arbitration scheme. When control of the bus is allocated to the single processor, the multiprocessor arbitration arbitrates among the processors who requested the bus. The bus protocol used includes a least recently used method for granting bus access to the multiple processors coupled with a means for giving one processor priority over the others for access to the bus. The protocol also includes protection from interruption for the respective processor in control of the bus for a preset period of time.

摘要翻译： 一种用于在可被并入设计成仅包括单个处理器的仲裁方案中的多个处理器之间进行仲裁的方法和装置。 该方法包括将每个处理器的各个总线请求整合到提供给单处理器仲裁方案的单个总线请求中。 当总线的控制被分配给单个处理器时，多处理器仲裁在请求总线的处理器之间进行仲裁。 所使用的总线协议包括最近最少使用的用于授予对多个处理器的总线访问的方法，该方法与用于给予一个处理器优先级的方式相比，用于访问总线。 该协议还包括在预设时间段内控制总线的各个处理器的中断保护。