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    INTEGRATED CLOCK GENERATOR AND METHOD THEREFOR
    23.
    发明申请
    INTEGRATED CLOCK GENERATOR AND METHOD THEREFOR 有权
    集成时钟发生器及其方法

    公开(公告)号：US20160226443A1

    公开(公告)日：2016-08-04

    申请号：US15096612

    申请日：2016-04-12

    Applicant: Silicon Laboratories Inc.

    Inventor： Aaron J. Caffee ,  Brian G. Drost ,  Hendricus de Ruijter

    IPC: H03B5/12 ,  H03L1/00

    CPC classification number: H03B5/1234 ,  H03B5/12 ,  H03B5/1265 ,  H03B5/36 ,  H03L1/00 ,  H03L1/026 ,  H03L7/02 ,  H03L7/087 ,  H03L7/095 ,  H03L7/183 ,  H03L7/1976 ,  H03L7/22 ,  H03L7/23

    Abstract: An integrated clock generator includes a tunable LC oscillator, a tunable frequency synthesizer, and a processor. The tunable LC oscillator has an input for receiving an oscillator control signal, and an output for providing an oscillator clock signal. The tunable frequency synthesizer has a clock input coupled to the output of the tunable LC oscillator, a control input for receiving a synthesizer control signal, and an output for providing a clock output signal. The processor has an input for receiving a data input signal, a first output for providing the oscillator control signal, and a second output for providing the synthesizer control signal. The processor provides the oscillator control signal and the synthesizer control signal such that the tunable frequency synthesizer generates the output clock signal at a frequency indicated by the data input signal, and provides the synthesizer control signal further in response to a dynamic condition.

    Abstract translation: 集成时钟发生器包括可调谐LC振荡器，可调频率合成器和处理器。 可调LC振荡器具有用于接收振荡器控制信号的输入端和用于提供振荡器时钟信号的输出端。 可调频率合成器具有耦合到可调谐LC振荡器的输出的时钟输入，用于接收合成器控制信号的控制输入和用于提供时钟输出信号的输出。 处理器具有用于接收数据输入信号的输入端，用于提供振荡器控制信号的第一输出端和用于提供合成器控制信号的第二输出端。 处理器提供振荡器控制信号和合成器控制信号，使得可调谐频率合成器以由数据输入信号指示的频率生成输出时钟信号，并且响应于动态条件进一步提供合成器控制信号。

    Load compensation to reduce deterministic jitter in clock applications
    24.
    发明授权
    Load compensation to reduce deterministic jitter in clock applications 有权

    公开(公告)号：US10530368B1

    公开(公告)日：2020-01-07

    申请号：US16191755

    申请日：2018-11-15

    Applicant: Silicon Laboratories Inc.

    Inventor： Aaron J. Caffee ,  Brian G. Drost

    IPC: H03K23/66 ,  H03K21/02

    Abstract: A clock circuit includes a circuit configured to use a regulated voltage on a regulated voltage node to provide a frequency modulated clock signal having a frequency vacillating between a first frequency and a second frequency. The clock circuit includes an auxiliary loading circuit coupled to the regulated voltage node and configured to selectively provide load compensation for a load difference of the circuit. The load difference is a difference between a first load corresponding to the first frequency and a second load corresponding to the second frequency. The circuit may include a frequency divider circuit configured to use the regulated voltage on the regulated voltage node to generate the frequency modulated clock signal by frequency dividing an input clock signal according to a divide value vacillating between a first divide value and a second divide value.

    Wide Range Glitchless Switchable Clock Divider With Modified 2/3 Divider Stages
    27.
    发明申请
    Wide Range Glitchless Switchable Clock Divider With Modified 2/3 Divider Stages 审中-公开

    公开(公告)号：US20180054203A1

    公开(公告)日：2018-02-22

    申请号：US15239552

    申请日：2016-08-17

    Applicant: Silicon Laboratories Inc.

    Inventor： Brian G. Drost

    IPC: H03K21/38 ,  H03K21/02

    Abstract: A divider includes 2/3 divider stages that may be turned off without toggling to extend the divide range of the divider while also reducing the impact of spurs on the divider output, and preserving the timing margin to update the divide ratio glitchlessly. A 2/3 divider stage responds to an input enable signal being deasserted and a modulus input signal being asserted to remain in a disabled state in which the divider stage does not toggle by ensuring storage elements outputs in the divider stage remain constant. The divider further selects an update clock for the divide ratio of the divider utilizing an output from a most downstream stage that remains enabled.

    Calibration of digital-to-time converter
    28.
    发明授权
    Calibration of digital-to-time converter 有权
    数字到时间转换器的校准

    公开(公告)号：US09531394B1

    公开(公告)日：2016-12-27

    申请号：US14745545

    申请日：2015-06-22

    Applicant: Silicon Laboratories Inc.

    Inventor： Aaron J. Caffee ,  Brian G. Drost

    IPC: H04L25/00 ,  H04L27/00 ,  H03L7/091 ,  H03L7/183 ,  H03L7/089

    CPC classification number: H03L7/091 ,  G06F1/022 ,  H03K5/135 ,  H03L7/081 ,  H03L7/0814 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/183 ,  H03L7/1976

    Abstract: A technique for calibrating a digital-to-time converter includes an apparatus including a digital-to-time converter configured to generate an output signal based on a digital code, an input signal, and a gain calibration signal. The output signal has edges linearly delayed from corresponding edges of the input signal based on the digital code. The digital code vacillates between an evaluation code and a calibration code. The apparatus includes a reference signal generator configured to provide a delayed version of the input signal. The delay of the reference signal generator is matched to a delay of the digital-to-time converter. The apparatus includes a calibration circuit configured to generate the gain calibration signal based on the output signal and the delayed version of the input signal. The calibration code may alternate between a first calibration delay code and a second calibration delay code.

    Abstract translation: 用于校准数字 - 时间转换器的技术包括一种包括数字 - 时间转换器的装置，其被配置为基于数字码，输入信号和增益校准信号来产生输出信号。 输出信号具有基于数字码从输入信号的相应边缘线性延迟的边缘。 数字代码在评估代码和校准代码之间摇摆。 该装置包括被配置为提供输入信号的延迟版本的参考信号发生器。 参考信号发生器的延迟与数字 - 时间转换器的延迟相匹配。 该装置包括校准电路，其被配置为基于输出信号和输入信号的延迟版本来生成增益校准信号。 校准代码可以在第一校准延迟代码和第二校准延迟代码之间交替。

    Noise-shaping time-to-digital converter
    29.
    发明授权
    Noise-shaping time-to-digital converter 有权
    噪声整形时间 - 数字转换器

    公开(公告)号：US09379879B1

    公开(公告)日：2016-06-28

    申请号：US14817129

    申请日：2015-08-03

    Applicant: Silicon Laboratories Inc.

    Inventor： Aaron J. Caffee ,  Brian G. Drost ,  James F. Parker

    IPC: H03L7/099 ,  H04L7/00 ,  H04L7/027 ,  G04F10/00

    CPC classification number: G04F10/005 ,  H03L7/091 ,  H03L7/23 ,  H03L2207/50

    Abstract: A noise-shaping time-to-digital converter has a large range and high resolution. The time-to-digital converter includes a phase detector configured to generate a phase error signal based on a phase-adjusted feedback signal and an input signal. The time-to-digital converter includes a loop filter configured to integrate the phase error signal and generate an analog integrated phase error signal. The time-to-digital converter includes an analog-to-digital converter configured to convert the analog integrated phase error signal to a digital phase error code. The time-to-digital converter includes a digital-to-time converter configured to convert at least a portion of the digital phase error code to a gating signal based on a reference signal and an enable signal. The time-to-digital converter includes a feedback circuit to generate the phase-adjusted feedback signal based on the reference signal and the gating signal.

    Abstract translation: 噪声整形时间 - 数字转换器具有大范围和高分辨率。 时间数字转换器包括相位检测器，其被配置为基于相位调整反馈信号和输入信号产生相位误差信号。 该时间 - 数字转换器包括环路滤波器，其被配置为对相位误差信号进行积分并产生模拟积分相位误差信号。 时间 - 数字转换器包括被配置为将模拟积分相位误差信号转换为数字相位误差代码的模拟 - 数字转换器。 时间 - 数字转换器包括数字 - 时间转换器，其被配置为基于参考信号和使能信号将数字相位误差代码的至少一部分转换为门控信号。 该时间 - 数字转换器包括基于参考信号和门控信号产生相位调整反馈信号的反馈电路。

    Calibration of digital-to-time converter
    30.
    发明授权
    Calibration of digital-to-time converter 有权

    公开(公告)号：US09369138B1

    公开(公告)日：2016-06-14

    申请号：US14745545

    申请日：2015-06-22

    Applicant: Silicon Laboratories Inc.

    Inventor： Aaron J. Caffee ,  Brian G. Drost

    IPC: H04L25/00 ,  H04L27/00 ,  H03L7/091 ,  H03L7/183 ,  H03L7/089

    Abstract: A technique for calibrating a digital-to-time converter includes an apparatus including a digital-to-time converter configured to generate an output signal based on a digital code, an input signal, and a gain calibration signal. The output signal has edges linearly delayed from corresponding edges of the input signal based on the digital code. The digital code vacillates between an evaluation code and a calibration code. The apparatus includes a reference signal generator configured to provide a delayed version of the input signal. The delay of the reference signal generator is matched to a delay of the digital-to-time converter. The apparatus includes a calibration circuit configured to generate the gain calibration signal based on the output signal and the delayed version of the input signal. The calibration code may alternate between a first calibration delay code and a second calibration delay code.

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