METHOD FOR ACCESSING FLASH MEMORY MODULE AND ASSOCIATED FLASH MEMORY CONTROLLER AND ELECTRONIC DEVICE

    公开(公告)号:US20210334039A1

    公开(公告)日:2021-10-28

    申请号:US16856008

    申请日:2020-04-22

    Abstract: The present invention discloses a method for accessing a flash memory module, wherein the flash memory module comprises a plurality of block, each block is implemented by a plurality of word lines, and each word line comprises a plurality of memory cells supporting a plurality of states. The method comprises the steps of: reading the memory cells of at least a first word line of a specific block of the plurality of blocks to obtain a cumulative distribution information of the states of the memory cells; determining a target decoding flow selected from at least a first decoding flow and a second decoding flow according to the cumulative distribution information; reading the memory cells of a second word line to obtain readout information of the second word line; and using the target decoding flow to decode the readout information of the second word line.

    FLASH MEMORY APPARATUS AND STORAGE MANAGEMENT METHOD FOR FLASH MEMORY

    公开(公告)号:US20210248036A1

    公开(公告)日:2021-08-12

    申请号:US17242326

    申请日:2021-04-28

    Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

    FLASH MEMORY APPARATUS AND STORAGE MANAGEMENT METHOD FOR FLASH MEMORY

    公开(公告)号:US20200233745A1

    公开(公告)日:2020-07-23

    申请号:US16841688

    申请日:2020-04-07

    Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

    Flash memory apparatus and storage management method for flash memory

    公开(公告)号:US10157098B2

    公开(公告)日:2018-12-18

    申请号:US15997674

    申请日:2018-06-04

    Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

    POWER SAVING FOR BIT FLIPPING DECODING ALGORITHM IN LDPC DECODER

    公开(公告)号:US20170288698A1

    公开(公告)日:2017-10-05

    申请号:US15083310

    申请日:2016-03-29

    Inventor: Jian-Dong Du

    CPC classification number: H03M13/1108 H03M13/1111 H03M13/1128 H03M13/3715

    Abstract: A method for determining when to end a bit flipping algorithm during hard decision soft decoding in a low density parity check (LDPC) decoder includes: selecting a certain number of iterations as a first threshold; when the first threshold is reached, determining a highest variable node codeword for each iteration performed so far; comparing the highest variable node codewords with a second threshold; and when the value of the highest variable node codewords is less than or equal to the second threshold, ending the bit flipping algorithm.

    Flash memory apparatus and storage management method for flash memory

    公开(公告)号:US12197285B2

    公开(公告)日:2025-01-14

    申请号:US18498069

    申请日:2023-10-31

    Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

    Method for improving read-retry of flash memory and related controller and storage device

    公开(公告)号:US11573734B2

    公开(公告)日:2023-02-07

    申请号:US16732333

    申请日:2020-01-01

    Abstract: The present invention proposes a method for managing a plurality of memory units in a flash memory module. The method includes: creating a programed timestamp corresponding to each first memory unit according to a data-written time of said each first memory unit; selecting a corresponding read-retry table for performing a read operation upon said each first memory unit according to the programed timestamp of said each first memory unit; and performing a first refresh operation according to program timestamps of first memory units that have been written with data.

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