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127 条记录 (耗时 0.038 秒)

    Current Compliant Sensing Architecture for Multilevel Phase Change Memory
    21.
    发明申请
    Current Compliant Sensing Architecture for Multilevel Phase Change Memory 有权
    多电平相变存储器的电流兼容传感架构

    公开(公告)号：US20080165570A1

    公开(公告)日：2008-07-10

    申请号：US11620432

    申请日：2007-01-05

    申请人： Thomas D. Happ ,  Hsiang Lan Lung ,  Thomas Nirschl

    发明人： Thomas D. Happ ,  Hsiang Lan Lung ,  Thomas Nirschl

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C13/004 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0054 ,  G11C2213/79

    摘要： A memory device and a method of reading the same includes a phase change element having a data state associated therewith that features maintaining the consistency of the data state of the phase change element in the presence of a read current. The memory circuit includes a sense amplifier that defines a sensing node. Circuitry selectively places the bit line in data communication with the sensing node, defining a selected bit line. A current source produces a read current, and a switch selectively applies the read current to the sensing node. Logic is in electrical communication with the sensing node to control the total energy to which the phase change material is subjected in the presence of the read current so that the data state remains consistent.

    摘要翻译： 存储器件及其读取方法包括具有与其相关联的数据状态的相变元件，其特征在于存在读取电流时维持相变单元的数据状态的一致性。 存储器电路包括限定感测节点的读出放大器。 电路选择性地将位线与感测节点进行数据通信，定义所选择的位线。 电流源产生读取电流，并且开关选择性地将读取电流施加到感测节点。 逻辑与感测节点电气通信，以在存在读取电流的情况下控制相变材料经受的总能量，使得数据状态保持一致。

    Combined read/write circuit for memory
    22.
    发明申请
    Combined read/write circuit for memory 审中-公开
    存储器的组合读/写电路

    公开(公告)号：US20080101110A1

    公开(公告)日：2008-05-01

    申请号：US11586115

    申请日：2006-10-25

    申请人： Thomas Happ ,  Thomas Nirschl

    发明人： Thomas Happ ,  Thomas Nirschl

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2013/0078 ,  G11C2213/79

    摘要： A memory device includes an array portion of resistive memory cells organized in rows and columns, wherein the rows correspond to word lines and the columns correspond to bit lines. The device further includes a combined read/write circuit associated with each respective bit line in the array portion configured to read from or write to a resistive memory cell associated with the respective bit line.

    摘要翻译： 存储器件包括以行和列组织的电阻存储器单元的阵列部分，其中行对应于字线，并且列对应于位线。 该设备还包括与阵列部分中的每个相应位线相关联的组合的读/写电路，其被配置为从与相应位线相关联的电阻式存储器单元读取或向其写入。

    SRAM memory cell and method for compensating a leakage current flowing into the SRAM memory cell
    26.
    发明申请
    SRAM memory cell and method for compensating a leakage current flowing into the SRAM memory cell 有权
    SRAM存储单元和用于补偿流入SRAM存储单元的漏电流的方法

    公开(公告)号：US20050281109A1

    公开(公告)日：2005-12-22

    申请号：US11137294

    申请日：2005-05-25

    申请人： Yannick Martelloni ,  Thomas Nirschl ,  Bernhard Wicht

    发明人： Yannick Martelloni ,  Thomas Nirschl ,  Bernhard Wicht

    IPC分类号： G11C7/02 ,  G11C11/412 ,  G11C11/419 ,  H01L27/11

    CPC分类号： G11C11/412

    摘要： An SRAM memory cell has at least one memory node and at least one selection transistor, which is electrically connected to the memory node, a first bit line and a first word line. Furthermore, the SRAM memory cell has means for compensating for a leakage current flowing into the SRAM memory cell. The means are designed in such a way that a current corresponding to the leakage current flows into the SRAM memory cell. In one exemplary embodiment, the means are formed as a transistor which is electrically connected to the first bit line and the second memory node, the first memory node being connected to the selection transistor.

    摘要翻译： SRAM存储单元具有至少一个存储器节点和至少一个选择晶体管，其电连接到存储器节点，第一位线和第一字线。 此外，SRAM存储单元具有用于补偿流入SRAM存储单元的漏电流的装置。 该装置被设计成使得对应于漏电流的电流流入SRAM存储单元。 在一个示例性实施例中，装置形成为电连接到第一位线和第二存储器节点的晶体管，第一存储器节点连接到选择晶体管。

    Current sense amplifier with replica bias scheme
    27.
    发明授权
    Current sense amplifier with replica bias scheme 有权
    电流检测放大器，具有复制偏置方案

    公开(公告)号：US08743630B2

    公开(公告)日：2014-06-03

    申请号：US13113427

    申请日：2011-05-23

    申请人： David Mueller ,  Thomas Nirschl

    发明人： David Mueller ,  Thomas Nirschl

    IPC分类号： G11C11/409

    CPC分类号： G11C7/065 ,  G11C7/062 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18

    摘要： Some embodiments of the present disclosure relate to a sense amplifier architecture that facilitates fast and accurate read operations. The sense amplifier architecture includes a folded cascode amplifier for its first sense amplifier stage, and a pre-charge circuit to establish a pre-charge condition for a senseline and a reference senseline of the sense amplifier. The pre-charge circuit and the folded cascode amplifier each include one or more cascode transistors of the same size and which receive the same bias voltage on a gate thereof. This architecture provides fast and accurate read operations in a relatively small footprint, thereby providing a good blend of cost and performance.

    摘要翻译： 本公开的一些实施例涉及促进快速和准确的读取操作的读出放大器架构。 感测放大器架构包括用于其第一读出放大器级的折叠共源共栅放大器和用于为感测放大器的感测线和参考感测线建立预充电状态的预充电电路。 预充电电路和折叠共源共栅放大器各自包括相同尺寸的一个或多个共源共栅晶体管，并且在其栅极上接收相同的偏置电压。 该架构在相对较小的占地面积中提供快速准确的读取操作，从而提供了成本和性能的良好组合。

    Method of operating phase-change memory
    28.
    发明授权
    Method of operating phase-change memory 有权
    操作相变存储器的方法

    公开(公告)号：US08670270B2

    公开(公告)日：2014-03-11

    申请号：US13402895

    申请日：2012-02-23

    申请人： Jan Otterstedt ,  Thomas Nirschl ,  Christian Peters ,  Michael Bollu ,  Wolf Allers ,  Michael Sommer

    发明人： Jan Otterstedt ,  Thomas Nirschl ,  Christian Peters ,  Michael Bollu ,  Wolf Allers ,  Michael Sommer

    IPC分类号： G11C11/00

    CPC分类号： G11C13/004 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2213/15 ,  G11C2213/79

    摘要： One or more embodiments may be related to a method of operating a phase-change memory element, comprising: providing the phase-change memory element, the phase-change memory element having a first terminal and a second terminal; causing a first current through the memory element from the first terminal to the second terminal; and causing a second current through the memory element from the second terminal to the first terminal, wherein the causing the first current programs the memory element from a first resistance state to a second resistance state and the causing the second current programs the memory element from the first resistance state to the second resistance state.

    摘要翻译： 一个或多个实施例可以涉及一种操作相变存储器元件的方法，包括：提供所述相变存储元件，所述相变存储元件具有第一端子和第二端子; 引起从第一端子到第二端子的存储元件的第一电流; 并且引起从第二端到第一端的存储元件的第二电流，其中使第一电流将存储器元件从第一电阻状态编程到第二电阻状态，并且使得第二电流从存储元件 第一电阻状态到第二电阻状态。

    Hybrid read scheme for multi-level data
    29.
    发明授权
    Hybrid read scheme for multi-level data 有权
    用于多级数据的混合读取方案

    公开(公告)号：US08509007B2

    公开(公告)日：2013-08-13

    申请号：US13405523

    申请日：2012-02-27

    申请人： Thomas Nirschl ,  Nigel Chan ,  Jan Otterstedt

    发明人： Thomas Nirschl ,  Nigel Chan ,  Jan Otterstedt

    IPC分类号： G11C7/06 ,  G11C16/04 ,  G11C16/06

    CPC分类号： G11C11/5642 ,  G06T7/223 ,  G06T2207/10016 ,  G06T2207/20016 ,  G06T2207/20021 ,  G11C2211/5634 ,  H04N19/53

    摘要： Some aspects of the present disclosure relate to a read circuit that uses a hybrid read scheme as set forth herein. In this hybrid read scheme, a state machine, at a first time in the read operation, sets a reference signal SRef to a first reference value to induce determination of a first comparison result. At a second subsequent time in the read operation, the state machine sets the reference signal SRef to a second reference value, which is based on the first comparison result. Setting the reference signal to the second reference value induces determination of a second comparison result. The first and second comparison results are then used to determine the digital value read from the memory cell.

    摘要翻译： 本公开的一些方面涉及使用如本文所阐述的混合读取方案的读取电路。 在该混合读取方案中，状态机在读取操作中的第一时间将参考信号SRef设置为第一参考值以引起第一比较结果的确定。 在读取操作的第二随后时间，状态机将参考信号SRef设置为基于第一比较结果的第二参考值。 将参考信号设置为第二参考值引起第二比较结果的确定。 然后使用第一和第二比较结果来确定从存储器单元读取的数字值。

    METHOD OF OPERATING PHASE-CHANGE MEMORY
    30.
    发明申请
    METHOD OF OPERATING PHASE-CHANGE MEMORY 有权
    操作相变记忆的方法

    公开(公告)号：US20130058159A1

    公开(公告)日：2013-03-07

    申请号：US13402895

    申请日：2012-02-23

    申请人： Jan Otterstedt ,  Thomas Nirschl ,  Christian Peters ,  Michael Bollu ,  Wolf Allers ,  Michael Sommer

    发明人： Jan Otterstedt ,  Thomas Nirschl ,  Christian Peters ,  Michael Bollu ,  Wolf Allers ,  Michael Sommer

    IPC分类号： G11C11/00

    CPC分类号： G11C13/004 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2213/15 ,  G11C2213/79

    摘要： One or more embodiments may be related to a method of operating a phase-change memory element, comprising: providing the phase-change memory element, the phase-change memory element having a first terminal and a second terminal; causing a first current through the memory element from the first terminal to the second terminal; and causing a second current through the memory element from the second terminal to the first terminal, wherein the causing the first current programs the memory element from a first resistance state to a second resistance state and the causing the second current programs the memory element from the first resistance state to the second resistance state.

    摘要翻译： 一个或多个实施例可以涉及一种操作相变存储器元件的方法，包括：提供所述相变存储元件，所述相变存储元件具有第一端子和第二端子; 引起从第一端子到第二端子的存储元件的第一电流; 并且引起从第二端到第一端的存储元件的第二电流，其中使第一电流将存储器元件从第一电阻状态编程到第二电阻状态，并且使得第二电流从存储元件 第一电阻状态到第二电阻状态。