公开(公告)号：US6133550A

公开(公告)日：2000-10-17

申请号：US140614

申请日：1998-08-26

申请人： Stewart K. Griffiths ,  Robert H. Nilson ,  Brad S. Mattson ,  Stephen E. Savas

发明人： Stewart K. Griffiths ,  Robert H. Nilson ,  Brad S. Mattson ,  Stephen E. Savas

IPC分类号： H01L21/677 ,  C23C16/46 ,  C23C16/54 ,  C30B25/10 ,  C30B31/12 ,  H01L21/00 ,  H01L21/205 ,  H01L21/26 ,  H01L21/265 ,  F27D11/00

CPC分类号： H01L21/67248 ,  C23C16/46 ,  C23C16/54 ,  C30B25/10 ,  C30B31/12 ,  H01L21/67109

摘要： An improved apparatus and method for thermal processing of semiconductor wafers. The apparatus and method provide the temperature stability and uniformity of a conventional batch furnace as well as the processing speed and reduced time-at-temperature of a lamp-heated rapid thermal processor (RTP). Individual wafers are rapidly inserted into and withdrawn from a furnace cavity held at a nearly constant and isothermal temperature. The speeds of insertion and withdrawal are sufficiently large to limit thermal stresses and thereby reduce or prevent plastic deformation of the wafer as it enters and leaves the furnace. By processing the semiconductor wafer in a substantially isothermal cavity, the wafer temperature and spatial uniformity of the wafer temperature can be ensured by measuring and controlling only temperatures of the cavity walls. Further, peak power requirements are very small compared to lamp-heated RTPs because the cavity temperature is not cycled and the thermal mass of the cavity is relatively large. Increased speeds of insertion and/or removal may also be used with non-isothermal furnaces.

公开(公告)号：US5225024A

公开(公告)日：1993-07-06

申请号：US750720

申请日：1991-08-22

申请人： Peter R. Hanley ,  Stephen E. Savas ,  Karl B. Levy ,  Neeta Jha ,  Kevin Donohoe

发明人： Peter R. Hanley ,  Stephen E. Savas ,  Karl B. Levy ,  Neeta Jha ,  Kevin Donohoe

IPC分类号： H01J37/32 ,  H05H1/46

CPC分类号： H01J37/32623 ,  H01J37/3266 ,  H05H1/46

摘要： Magnetic confinement of electrons in a plasma reactor is effected using electro-magnetic coils and other magnets which generate respective magnetic fields which are mutually opposed and substantially orthogonal on their common axis to the major plane of a wafer being processed, instead of being aligned and parallel to the major plane as in prior magnetically enhanced plasma reactors. The respective magnetic fields combine to yield a net magnetic field which is nearly parallel to the wafer away from the magnetic axis so that electrons are confined in the usual manner. In addition, a magnetic mirror provides confinement near the magnetic axis. The E.times.B cross product defines a circumferential drift velocity urging electrons about a closed path about the magnetic axis. The magnetic and cross-product forces on plasma electrons have a rotational symmetry which enhances reaction uniformity across the wafer; this contrasts with the prior art in which lateral drift velocity disturbs plasma symmetry and thus reaction uniformity. Furthermore, the disclosed field geometry permits stronger electron confinement which enhances plasma reaction rates.

摘要翻译： 使用电磁线圈和其它磁体来实现等离子体反应器中的电子的限制，这些磁体产生各自的磁场，这些磁场在它们的公共轴线上相互对置并且基本上正交于被处理的晶片的主平面，而不是对准和平行 到现有的磁增强等离子体反应器中的主平面。 相应的磁场结合起来产生一个净磁场，该磁场几乎平行于离开磁轴的晶片，使得电子以通常的方式被限制。 此外，磁镜在磁轴附近提供约束。 ExB交叉乘积定义围绕磁轴围绕闭合路径推动电子的周向漂移速度。 等离子体电子的磁性和交叉积分力具有提高晶片反应均匀性的旋转对称性; 这与现有技术形成对比，其中横向漂移速度扰乱等离子体对称性并因此干扰反应均匀性。 此外，所公开的场几何形式允许更强的电子限制，这增强了等离子体反应速率。

公开(公告)号：US20100151694A1

公开(公告)日：2010-06-17

申请号：US12334425

申请日：2008-12-12

申请人： Bruce W. Peuse ,  Yaozhi Hu ,  Paul Janis Timans ,  Guangcai Xing ,  Wilfried Lerch ,  Sing-Pin Tay ,  Stephen E. Savas ,  Georg Roters ,  Zsolt Nenyei ,  Ashok Sinha

发明人： Bruce W. Peuse ,  Yaozhi Hu ,  Paul Janis Timans ,  Guangcai Xing ,  Wilfried Lerch ,  Sing-Pin Tay ,  Stephen E. Savas ,  Georg Roters ,  Zsolt Nenyei ,  Ashok Sinha

IPC分类号： H01L21/316 ,  C23C16/00

CPC分类号： H01L21/31654 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/67115 ,  H01L21/67248 ,  H01L21/68771

摘要： Plasma assisted low temperature radical oxidation is described. The oxidation is selective to metals or metal oxides that may be present in addition to the silicon being oxidized. Selectivity is achieved by proper selection of process parameters, mainly the ratio of H2 to O2 gas. The process window may be enlarged by injecting H2O steam into the plasma, thereby enabling oxidation of silicon in the presence of TiN and W, at relatively low temperatures. Selective oxidation is improved by the use of an apparatus having remote plasma and flowing radicals onto the substrate, but blocking ions from reaching the substrate.

摘要翻译： 描述了等离子体辅助低温自由基氧化。 除了被氧化的硅之外，氧化对于可能存在的金属或金属氧化物是选择性的。 选择性通过适当选择工艺参数来实现，主要是H2与O2气的比例。 可以通过将H 2 O蒸汽注入到等离子体中来扩大工艺窗口，从而可以在相对低的温度下在TiN和W的存在下氧化硅。 通过使用具有远离等离子体和流动基团的装置到衬底上但阻止离子到达衬底的装置来改善选择性氧化。

公开(公告)号：US06342691B1

公开(公告)日：2002-01-29

申请号：US09439833

申请日：1999-11-12

申请人： Kristian E. Johnsgard ,  Jean-François Daviet ,  James A. Givens ,  Stephen E. Savas ,  Brad S. Mattson ,  Ashur J. Atanos

发明人： Kristian E. Johnsgard ,  Jean-François Daviet ,  James A. Givens ,  Stephen E. Savas ,  Brad S. Mattson ,  Ashur J. Atanos

IPC分类号： F27B514

CPC分类号： H01L21/67115 ,  C30B31/12

摘要： A semiconductor substrate processing system and method of using a stable heating source with a large thermal mass relative to conventional lamp heating systems. The system dimensions and processing parameters are selected to provide a substantial heat flux to the substrate while reducing the potential of heat loss to the surrounding environment, particularly from the edges of the heat source and substrate. Aspects of the present invention include a dual resistive heater system comprising a base or primary heater, surrounded by a peripheral or edge heater. The impedance of the edge heater may be substantially matched to that of the primary heater such that a single power supply may be used to supply power to both heaters. Both resistive heaters deliver heat to a heated block, and the heaters and heated block are substantially enclosed within an insulated cavity. The walls of the insulated cavity may include multiple layers of insulation, and these layers may be substantially concentrically arranged. The innermost layers may comprise silicon carbide coated graphite; the outer layers may comprise opaque quartz. An embodiment of the invention includes a vacuum spool having a large conduction pathway for exhausting gases from the region of the chamber containing the resistive heaters, and a small conduction pathway for removing gases from other regions of the chamber. Temperature measurement sensors include thermocouples and optical pyrometers, with the advantage that a thermocouple may be used to calibrate an optical pyrometer in situ. An insulating shutter may be used to insulate the port through which substrates are inserted into the insulated and heated cavity. Support posts and gas injectors may include ports for optical pyrometers.

摘要翻译： 相对于传统的灯加热系统，半导体衬底处理系统和使用具有大热质量的稳定的热源的方法。 选择系统尺寸和处理参数以向基板提供实质的热通量，同时减少对周围环境，特别是从热源和基板的边缘的热损失的潜力。 本发明的方面包括双电阻加热器系统，其包括被周边或边缘加热器包围的基座或主加热器。 边缘加热器的阻抗可以与初级加热器的阻抗基本匹配，使得单个电源可以用于向两个加热器供电。 两个电阻加热器将热量传递到加热块，并且加热器和加热块基本上封闭在绝缘腔内。 绝缘腔的壁可以包括多层绝缘体，并且这些层可以基本上同心地布置。 最内层可包括碳化硅涂覆的石墨; 外层可以包括不透明的石英。 本发明的实施例包括具有用于从包含电阻加热器的室的区域排出气体的大的传导路径的真空阀芯，以及用于从腔室的其它区域去除气体的小的传导路径。 温度测量传感器包括热电偶和光学高温计，其优点是热电偶可用于原位校准光学高温计。 可以使用绝缘快门来将通过哪个基板插入绝缘和加热腔的端口绝缘。 支撑柱和气体注入器可以包括用于光学高温计的端口。

公开(公告)号：US06253704B1

公开(公告)日：2001-07-03

申请号：US09398553

申请日：1999-09-17

申请人： Stephen E. Savas

发明人： Stephen E. Savas

IPC分类号： C23C1600

CPC分类号： H01J37/321 ,  H01J37/32082 ,  H01J37/32706 ,  H01J2237/004 ,  H01J2237/3345

摘要： Apparatus and method for an improved etch process. A power source alternates between high and low power cycles to produce and sustain a plasma discharge. Preferably, the high power cycles couple sufficient power into the plasma to produce a high density of ions (≳1011cm−3) for etching. Preferably, the low power cycles allow electrons to cool off to reduce the average random (thermal) electron velocity in the plasma. Preferably, the low power cycle is limited in duration as necessary to prevent excessive plasma loss to the walls or due to recombination of negative and positive ions. It is an advantage of these and other aspects of the present invention that average electron thermal velocity is reduced, so fewer electrons overcome the plasma sheath and accumulate on substrate or mask layer surfaces. A separate power source alternates between high and low power cycles to accelerate ions toward the substrate being etched. In one embodiment, a strong bias is applied to the substrate in short bursts. Preferably, multiple burst occur during the average transit time for an ion to cross the plasma sheath and reach the substrate surface. Ions are pulsed toward the surface for etching. These ions are not deflected into sidewalls as readily as ions in conventional low energy etch processes due to reduced charge buildup and the relatively low duty cycle of power used to pulse ions toward the substrate surface.

摘要翻译： 用于改进蚀刻工艺的装置和方法。 电源在高功率和低功率周期之间交替产生和维持等离子体放电。 优选地，高功率循环将足够的功率耦合到等离子体中以产生用于蚀刻的高密度离子（>〜1011cm-3）。 优选地，低功率周期允许电子冷却以降低等离子体中的平均随机（热）电子速度。 优选地，低功率循环的持续时间受到限制，以防止对壁的过度等离子体损失或由于负离子和正离子的复合。 本发明的这些和其它方面的优点是平均电子热速度降低，因此较少的电子克服了等离子体鞘并积聚在衬底或掩模层表面上。 单独的电源在高功率和低功率循环之间交替，以将离子加速朝向被蚀刻的衬底。 在一个实施例中，以短脉冲串将强偏压施加到衬底。 优选地，在平均通过时间期间发生多次爆发，以使离子穿过等离子体护套并到达衬底表面。 离子脉冲朝表面进行蚀刻。 这些离子由于电荷累积减少和脉冲离子朝向衬底表面的相对低的功率占空比而不会像传统的低能量蚀刻工艺中的离子一样容易地偏转到侧壁中。

公开(公告)号：US06236023B1

公开(公告)日：2001-05-22

申请号：US09351258

申请日：1999-07-12

申请人： Stephen E. Savas ,  Martin L. Hammond ,  Jean-François Daviet

发明人： Stephen E. Savas ,  Martin L. Hammond ,  Jean-François Daviet

IPC分类号： F27B514

CPC分类号： C30B31/10 ,  C23C16/4405 ,  C30B25/08 ,  Y10S438/905

摘要： A method for in-situ cleaning of a hot wall RTP system. Internal components are heated to high temperatures above 500° C. A halocarbon gas, inert gas and oxidizing gas are flowed through the reactor for a period which may exceed 20 minutes and then purged to remove contaminants.

摘要翻译： 一种用于原位清洗热壁RTP系统的方法。 将内部组分加热至高于500℃的高温。卤代烃气体，惰性气体和氧化气体通过反应器流过可能超过20分钟的时间，然后被吹扫以除去污染物。

公开(公告)号：US06198074B1

公开(公告)日：2001-03-06

申请号：US08923661

申请日：1997-09-04

申请人： Stephen E. Savas

发明人： Stephen E. Savas

IPC分类号： H01L21205

CPC分类号： C23C16/463 ,  C23C16/46 ,  H01L21/67103 ,  Y10S414/135

摘要： A system and method for thermally processing a substrate. A substrate is heated to a processing temperature at which the substrate is susceptible to plastic deformation or slip. An insulating cover may be removed to initially cool the substrate below such temperature before removal from the system. Gas pressure may also be adjusted to enhance heat transfer during processing and decrease heat transfer prior to removal of the substrate. Susceptors or surfaces for cooling the substrate may also be included in the system. The substrate may be transferred from a heating surface to a cooling surface by moving or rotating the substrate through warm transitional regions to avoid slip.

摘要翻译： 一种用于热处理衬底的系统和方法。 将基板加热到基板容易发生塑性变形或滑动的加工温度。 可以去除绝缘盖以在从系统移除之前首先将衬底冷却至低于该温度。 也可以调节气体压力以增强加工期间的热传递，并且在去除基底之前减少热传递。 用于冷却衬底的吸收体或表面也可以包括在系统中。 衬底可以通过移动或旋转衬底通过温暖的过渡区域从加热表面转移到冷却表面，以避免滑动。

公开(公告)号：US06143129A

公开(公告)日：2000-11-07

申请号：US118281

申请日：1998-07-17

申请人： Stephen E. Savas ,  Brad S. Mattson ,  Martin L. Hammond ,  Steven C. Selbrede

发明人： Stephen E. Savas ,  Brad S. Mattson ,  Martin L. Hammond ,  Steven C. Selbrede

IPC分类号： H05H1/46 ,  C23C16/50 ,  C23F4/00 ,  H01J37/32 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065

CPC分类号： H01J37/32871 ,  H01J37/321 ,  H01J37/32357 ,  H01J37/32422 ,  H01J37/32706 ,  Y10S156/912

摘要： A plasma reactor and methods for processing semiconductor wafers are described. Gases are introduced into a reactor chamber. An induction coil surrounds the reactor chamber. RF power is applied to the induction coil and is inductively coupled into the reactor chamber causing a plasma to form. A split Faraday shield is interposed between the induction coil and the reactor chamber to substantially block the capacitive coupling of energy into the reactor chamber which may modulate the plasma potential. The configuration of the split Faraday shield may be selected to control the level of modulation of the plasma potential. For etch processes, a separate powered electrode may be used to accelerate ions toward a wafer surface. For isotropic etching processes, charged particles may be filtered from the gas flow, while a neutral activated species passes unimpeded to a wafer surface.

公开(公告)号：US5983828A

公开(公告)日：1999-11-16

申请号：US727209

申请日：1996-10-08

申请人： Stephen E. Savas

发明人： Stephen E. Savas

IPC分类号： H01J37/32 ,  C23C16/00

CPC分类号： H01J37/321 ,  H01J37/32082 ,  H01J37/32706 ,  H01J2237/004 ,  H01J2237/3345

摘要： Apparatus and method for an improved etch process. A power source alternates between high and low power cycles to produce and sustain a plasma discharge. Preferably, the high power cycles couple sufficient power into the plasma to produce a high density of ions (>10.sup.11 cm.sup.-3) for etching. Preferably, the low power cycles allow electrons to cool off to reduce the average random (thermal) electron velocity in the plasma. Preferably, the low power cycle is limited in duration as necessary to prevent excessive plasma loss to the walls or due to recombination of negative and positive ions. It is an advantage of these and other aspects of the present invention that average electron thermal velocity is reduced, so fewer electrons overcome the plasma sheath and accumulate on substrate or mask layer surfaces. A separate power source alternates between high and low power cycles to accelerate ions toward the substrate being etched. In one embodiment, a strong bias is applied to the substrate in short bursts. Preferably, multiple burst occur during the average transit time for an ion to cross the plasma sheath and reach the substrate surface. Ions are pulsed toward the surface for etching. These ions are not deflected into sidewalls as readily as ions in conventional low energy etch processes due to reduced charge buildup and the relatively low duty cycle of power used to pulse ions toward the substrate surface.

摘要翻译： 用于改进蚀刻工艺的装置和方法。 电源在高功率和低功率周期之间交替产生和维持等离子体放电。 优选地，高功率循环将足够的功率耦合到等离子体中以产生用于蚀刻的高密度离子（+ E，ut1 + EE1011cm-3）。 优选地，低功率周期允许电子冷却以降低等离子体中的平均随机（热）电子速度。 优选地，低功率循环的持续时间受到限制，以防止对壁的过度等离子体损失或由于负离子和正离子的复合。 本发明的这些和其它方面的优点是平均电子热速度降低，因此较少的电子克服了等离子体鞘并积聚在衬底或掩模层表面上。 单独的电源在高功率和低功率循环之间交替，以将离子加速朝向被蚀刻的衬底。 在一个实施例中，以短脉冲串将强偏压施加到衬底。 优选地，在平均通过时间期间发生多次爆发，以使离子穿过等离子体护套并到达衬底表面。 离子脉冲朝表面进行蚀刻。 这些离子由于电荷累积减少和脉冲离子朝向衬底表面的相对低的功率占空比而不会像传统的低能量蚀刻工艺中的离子一样容易地偏转到侧壁中。

公开(公告)号：US5811022A

公开(公告)日：1998-09-22

申请号：US340696

申请日：1994-11-15

申请人： Stephen E. Savas ,  Brad S. Mattson

发明人： Stephen E. Savas ,  Brad S. Mattson

IPC分类号： H05H1/46 ,  C23C16/50 ,  C23F4/00 ,  H01J37/32 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H05H1/00

CPC分类号： H01J37/32871 ,  H01J37/321 ,  H01J37/32357 ,  H01J37/32422 ,  H01J37/32706 ,  Y10S156/912

摘要： A plasma reactor and methods for processing semiconductor wafers are described. Gases are introduced into a reactor chamber. An induction coil surrounds the reactor chamber. RF power is applied to the induction coil and is inductively coupled into the reactor chamber causing a plasma to form. A split Faraday shield is interposed between the induction coil and the reactor chamber to substantially block the capacitive coupling of energy into the reactor chamber which may modulate the plasma potential. The configuration of the split Faraday shield may be selected to control the level of modulation of the plasma potential. For etch processes, a separate powered electrode may be used to accelerate ions toward a wafer surface. For isotropic etching processes, charged particles may be filtered from the gas flow, while a neutral activated species passes unimpeded to a wafer surface.