公开(公告)号：US06557053B1

公开(公告)日：2003-04-29

申请号：US09477179

申请日：2000-01-04

申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Michael Raymond Trombley ,  Fabrice Jean Verplanken

发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Michael Raymond Trombley ,  Fabrice Jean Verplanken

IPC分类号： G06F1314

CPC分类号： G06F13/1673

摘要： A bandwidth conserving queue manager for a FIFO buffer is provided, preferably on an ASIC chip and preferably including separate DRAM storage that maintains a FIFO queue which can extend beyond the data storage space of the FIFO buffer to provide additional data storage space as needed. FIFO buffers are used on the ASIC chip to store and retrieve multiple queue entries. As long as the total size of the queue does not exceed the storage available in the buffers, no additional data storage is needed. However, when some predetermined amount of the buffer storage space in the FIFO buffers is exceeded, data are written to and read from the additional data storage, and preferably in packets which are of optimum size for maintaining peak performance of the data storage device and which are written to the data storage device in such a way that they are queued in a first-in, first-out (FIFO) sequence of addresses. Preferably, the data are written to and are read from the DRAM in burst mode.

摘要翻译： 提供了用于FIFO缓冲器的带宽保存队列管理器，优选地在ASIC芯片上，并且优选地包括分离的DRAM存储器，其维持FIFO队列，其可以超出FIFO缓冲器的数据存储空间，以根据需要提供附加的数据存储空间。 在ASIC芯片上使用FIFO缓冲器来存储和检索多个队列条目。 只要队列的总大小不超过缓冲区中可用的存储空间，则不需要额外的数据存储。 然而，当超过FIFO缓冲器中的一些预定量的缓冲存储空间时，数据被写入附加数据存储器并从其中读出，并且优选地是具有用于保持数据存储设备的峰值性能的最佳尺寸的数据包，以及哪个 被写入数据存储设备，使得它们以先入先出（FIFO）地址序列排队。 优选地，以突发模式将数据写入DRAM并从DRAM读取。

公开(公告)号：US07872968B2

公开(公告)日：2011-01-18

申请号：US11608295

申请日：2006-12-08

申请人： Brahmanand Kumar Gorti ,  Marco Heddes ,  Clark Debs Jeffries ,  Andreas Kind ,  Michael Steven Siegel

发明人： Brahmanand Kumar Gorti ,  Marco Heddes ,  Clark Debs Jeffries ,  Andreas Kind ,  Michael Steven Siegel

IPC分类号： G01R31/08 ,  H04L12/28

CPC分类号： H04L47/6215 ,  H04L47/10 ,  H04L47/2416 ,  H04L47/2433 ,  H04L47/30 ,  H04L47/32 ,  H04L47/50 ,  H04L47/52 ,  H04L47/56

摘要： A method and system for transmitting packets in a packet switching network. Packets received by a packet processor may be prioritized based on the urgency to process them. Packets that are urgent to be processed may be referred to as real-time packets. Packets that are not urgent to be processed may be referred to as non-real-time packets. Real-time packets have a higher priority to be processed than non-real-time packets. A real-time packet may either be discarded or transmitted into a real-time queue based upon its value priority, the minimum and maximum rates for that value priority and the current real-time queue congestion conditions. A non-real-time packet may either be discarded or transmitted into a non-real-time queue based upon its value priority, the minimum and maximum rates for that value priority and the current real-time and non-real-time queue congestion conditions.

摘要翻译： 一种用于在分组交换网络中传送分组的方法和系统。 可以基于处理它们的紧急性来优先考虑由分组处理器接收的分组。 紧急处理的数据包可以称为实时数据包。 不紧急处理的数据包可能被称为非实时数据包。 实时数据包的优先级要高于非实时数据包。 可以根据其值优先级，该值优先级的最小和最大速率以及当前实时队列拥塞条件，将实时分组丢弃或传输到实时队列中。 可以基于其值优先级，该值优先级的最小和最大速率以及当前的实时和非实时队列拥塞将非实时分组丢弃或发送到非实时队列 条件。

公开(公告)号：US07865697B2

公开(公告)日：2011-01-04

申请号：US12037948

申请日：2008-02-27

申请人： Zorik Machulsky ,  Julian Satran ,  Leah Shalev ,  Michael Steven Siegel ,  Gregory Scott Still ,  James Xenidis

发明人： Zorik Machulsky ,  Julian Satran ,  Leah Shalev ,  Michael Steven Siegel ,  Gregory Scott Still ,  James Xenidis

IPC分类号： G06F15/76 ,  G06F15/80

CPC分类号： G06F9/5044 ,  G06F9/3879 ,  G06F2209/509

摘要： A mechanism enabling a processor in a multiprocessor complex to function as a coprocessor to execute a specific function. The method includes a mechanism for activating a coprocessor to function as a coprocessor as well as a mechanism to execute a coprocessor request on the system. The present invention also provides a mechanism for efficient processor to processor communication for processors coupled to a common bus. Overall system performance is enhanced by significantly reducing the use of hardware interrupts for processor to processor communication.

摘要翻译： 使多处理器复合体中的处理器能够用作协处理器来执行特定功能的机制。 该方法包括用于激活协处理器以用作协处理器的机制以及在系统上执行协处理器请求的机制。 本发明还提供了一种用于处理器与处理器通信的有效处理器的机制，用于处理器与公共总线相连。 通过显着减少处理器到处理器通信的硬件中断的使用，整体系统性能得到增强。

公开(公告)号：US20100262735A1

公开(公告)日：2010-10-14

申请号：US12423355

申请日：2009-04-14

申请人： Lakshminarayana Baba Arimilli ,  Brian Mitchell Bass ,  David Wayne Cummings ,  Bernard Charles Drerup ,  Guy Lynn Guthrie ,  Ronald Nick Kalla ,  Hugh Shen ,  Michael Steven Siegel ,  William John Starke ,  Derek Edward Williams

发明人： Lakshminarayana Baba Arimilli ,  Brian Mitchell Bass ,  David Wayne Cummings ,  Bernard Charles Drerup ,  Guy Lynn Guthrie ,  Ronald Nick Kalla ,  Hugh Shen ,  Michael Steven Siegel ,  William John Starke ,  Derek Edward Williams

IPC分类号： G06F13/14 ,  G06F12/00 ,  G06F12/08

CPC分类号： G06F12/1458 ,  G06F9/30047 ,  G06F9/30087 ,  G06F12/0893

摘要： A technique for triggering a system bus write command with user code includes identifying a specific store-type instruction in a user instruction sequence. The specific store-type instruction is converted into a specific request-type command, which is configured to include core permission controls (that are stored in core configuration registers of a processor core by a trusted kernel) and user created data (stored in a cache memory). Slave devices are configured through register space (that is only accessible by the trusted kernel) with respective slave permission controls. The specific request-type command is then transmitted from the cache memory, via a system bus. In this case, the slave devices that receive the specific request-type command (via the system bus) process the specific request-type command when the core permission controls are the same as the respective slave permission controls.

摘要翻译： 用户代码触发系统总线写命令的技术包括识别用户指令序列中的特定存储型指令。 特定存储型指令被转换成特定的请求类型命令，其被配置为包括核心权限控制（存储在可信内核的处理器核心的核心配置寄存器中）和用户创建的数据（存储在高速缓存中） 记忆）。 从设备通过具有相应从属权限控制的寄存器空间（可由可信内核访问）进行配置。 然后，经由系统总线从高速缓冲存储器发送特定的请求类型命令。 在这种情况下，当核心权限控制与相应从属许可控制相同时，接收特定请求类型命令（通过系统总线）的从设备处理特定请求类型命令。

公开(公告)号：US07167471B2

公开(公告)日：2007-01-23

申请号：US09940758

申请日：2001-08-28

申请人： Jean Louis Calvignac ,  Gordon Taylor Davis ,  Marco Heddes ,  Michael Steven Siegel

发明人： Jean Louis Calvignac ,  Gordon Taylor Davis ,  Marco Heddes ,  Michael Steven Siegel

IPC分类号： H04L12/56

CPC分类号： H04L49/3009 ,  G11C15/00 ,  H04L45/745 ,  H04L45/7453 ,  H04L49/90

摘要： A method and system for identifying a data structure associated with a packet of data. A processor internal to a packet processor may extract one or more fields in a packet header field of a received packet of data to generate a search key. The internal processor may then be configured to select which table, e.g., routing table, quality of service table, filter table, needs to be accessed using the search key in order to process the received packet of data. A determination may then be made by the internal processor as to whether a CAM or a hash table and a Patricia Tree are used to identify the data structure associated with the received packet of data. Based on table definitions in a register, the internal processor may make such a determination.

摘要翻译： 一种用于识别与数据包相关联的数据结构的方法和系统。 分组处理器内部的处理器可以提取接收到的数据分组的分组报头字段中的一个或多个字段以生成搜索关键字。 然后可以将内部处理器配置为选择哪个表，例如路由表，服务质量表，过滤表，需要使用搜索关键字进行访问，以便处理接收的数据分组。 然后内部处理器可以确定CAM或散列表和Patricia Tree是否用于标识与所接收的数据分组相关联的数据结构。 根据寄存器中的表定义，内部处理器可以作出这样的确定。

公开(公告)号：US07139753B2

公开(公告)日：2006-11-21

申请号：US10650327

申请日：2003-08-28

申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Antonios Maragkos ,  Piyush Chunilal Patel ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Antonios Maragkos ,  Piyush Chunilal Patel ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

IPC分类号： G06F7/00 ,  H04L12/28

CPC分类号： H04L45/742 ,  H04L45/7453 ,  Y10S707/99933 ,  Y10S707/99934 ,  Y10S707/99935 ,  Y10S707/99936 ,  Y10S707/99937 ,  Y10S707/99943 ,  Y10S707/99945

摘要： Novel data structures, methods and apparatus for finding a full match between a search pattern and a pattern stored in a leaf of the search tree. A key is input, a hash function is performed on the key, a direct table (DT) is accessed, and a tree is walked through pattern search control blocks (PSCBs) until reaching a leaf. The search mechanism uses a set of data structures that can be located in a few registers and regular memory, and then used to build a Patricia tree structure that can be manipulated by a relatively simple hardware macro. Both keys and corresponding information needed for retrieval are stored in the Patricia tree structure. The hash function provides an n->n mapping of the bits of the key to the bits of the hash key. The data structure that is used to store the hash key and the related information in the tree is called a leaf. Each leaf corresponds to a single key that matches exactly with the input key. The leaf contains the key as well as additional information. The length of the leaf is programmable, as is the length of the key. The leaf is stored in random access memory and is implemented as a single memory entry. If the key is located in the direct table then it is called a direct leaf.

摘要翻译： 用于在搜索图案和存储在搜索树的叶中的模式之间找到完全匹配的新型数据结构，方法和装置。 键输入，对密钥执行哈希函数，访问直接表（DT），并通过模式搜索控制块（PSCB），树直到达到叶。 搜索机制使用一组可以位于几个寄存器和常规内存中的数据结构，然后用于构建可由相对简单的硬件宏操作的Patricia树结构。 检索所需的两个密钥和相应的信息都存储在Patricia树结构中。 散列函数提供密钥的比特到散列密钥的比特的n> n映射。 用于存储散列键和树中相关信息的数据结构称为叶。 每个叶对应于与输入键完全匹配的单个键。 叶包含关键以及其他信息。 叶片的长度是可编程的，密钥的长度也是可编程的。 叶存储在随机存取存储器中，并被实现为单个存储器条目。 如果键位于直接表中，则称为直接叶。

公开(公告)号：US07126963B2

公开(公告)日：2006-10-24

申请号：US10154308

申请日：2002-05-23

申请人： Mohammad Peyravian ,  Mark Anthony Rinaldi ,  Ravinder Kumar Sabhiki ,  Michael Steven Siegel

发明人： Mohammad Peyravian ,  Mark Anthony Rinaldi ,  Ravinder Kumar Sabhiki ,  Michael Steven Siegel

IPC分类号： H04B7/212

CPC分类号： H04L47/724 ,  H04L41/0896 ,  H04L41/5003 ,  H04L47/26 ,  H04L47/70 ,  H04L47/829

摘要： A Resource Reservation System includes a Token Generation Unit (TGU) which generates and circulates among nodes of a communications system a Slotted Token (SLT) message having sub-fields to carry identification number for each input port in a node and the resource available for each input port. On receiving the message the Resource Control Unit (RCU) in each node can write port identification number, available resource in appropriate sub-fields of the SLT message, and reserve resources in other nodes by adjusting information in the sub-field associated with the other nodes.

公开(公告)号：US07106730B1

公开(公告)日：2006-09-12

申请号：US09546833

申请日：2000-04-11

申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

IPC分类号： H04L12/56

CPC分类号： H04L49/30

摘要： A network device including an ingress processor and egress processor which receives frames of data over the network on an input port, and transfers it to an appropriate output port. The received frame is processed by an ingress processor which prepares an intra-switch frame for delivery to an egress processor serving a relevant output port of the switch. The intra-switch frame includes a frame header having parameters which have been determined by the ingress processor, as well as data indicating an address for the egress processor for beginning processing of the frame. By identifying to the egress processor processing which has already taken place, the egress processor is relieved of any redundant processing of the frame. The egress processor provides a hardware frame classifier which decodes the information contained in the intra-frame header to derive parameters which have been previously computed as well as a starting address for the egress processor. By reducing the amount of redundant processing of the egress processor, total device throughput delay is reduced.

摘要翻译： 一种网络设备，包括入口处理器和出口处理器，其在输入端口上通过网络接收数据帧，并将其传送到适当的输出端口。 接收到的帧由入口处理器处理，入口处理器准备一个内部交换帧，用于传送到服务于交换机的相关输出端口的出口处理器。 帧内切换帧包括具有由入口处理器确定的参数的帧报头，以及指示用于开始处理该帧的出口处理器的地址的数据。 通过识别已经发生的出口处理器处理，出口处理器免除了帧的任何冗余处理。 出口处理器提供硬件帧分类器，其对包含在帧内报头中的信息进行解码以导出先前已经计算的参数以及出口处理器的起始地址。 通过减少出口处理器的冗余处理量，减少了总设备吞吐量延迟。

公开(公告)号：US07072299B2

公开(公告)日：2006-07-04

申请号：US09933526

申请日：2001-08-20

申请人： Brian Mitchell Bass ,  Clark Debs Jeffries ,  Michael Steven Siegel

发明人： Brian Mitchell Bass ,  Clark Debs Jeffries ,  Michael Steven Siegel

IPC分类号： H04J1/16

CPC分类号： H04L47/30 ,  H04L47/10 ,  H04L47/29 ,  H04L47/39

摘要： A receiver may be adapted to prevent overflow or underflow of its data storage by generating a transmit rate value as a feedback to the sender. Speed adjustments are performed periodically with a fixed time period denoted by Dt. Transmission rates are explicitly 0, Max/2, and Max. The receiver queue is itself drained at a rate R that at any time satisfies 0

摘要翻译： 接收机可以适于通过生成发送速率值作为对发送者的反馈来防止其数据存储器的溢出或下溢。 以Dt表示的固定时间段周期性地执行速度调节。 传输速率明确为0，Max / 2和Max。 接收器队列本身以在任何时间满足0 <= R <= Max的速率R排出。 接收机存储队列的占用等级由Q表示。接收队列的最大容量被指定为Qmax，所以在任何时候，0≤Q≤Qmax。 确定接收器队列值Q的电平的两个阈值T 1和T 2（具有0

公开(公告)号：US06862292B1

公开(公告)日：2005-03-01

申请号：US09548910

申请日：2000-04-13

申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

IPC分类号： H04L12/56 ,  H04Q11/04 ,  H04L12/28

CPC分类号： H04Q11/0478 ,  H04L47/2425 ,  H04L47/50 ,  H04L47/52 ,  H04L47/627 ,  H04L2012/5636 ,  H04L2012/5649 ,  H04L2012/5651 ,  H04L2012/5679 ,  H04L2012/5681

摘要： A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. The priorities in the preferred embodiment include a low latency service, a minimum bandwidth, a weighted fair queueing and a system for preventing a user from continuing to exceed his service levels over an extended period. The present invention includes a plurality of calendars with different service rates to allow a user to select the service rate which he desires. If a customer has chosen a high bandwidth for service, the customer will be included in a calendar which is serviced more often than if the customer has chosen a lower bandwidth.

摘要翻译： 一种将信息单元从网络处理器移动到数据传输网络的系统和方法，其以容纳几个不同级别的服务的优先顺序排列。 本发明包括一种方法和系统，用于根据存储的与信息单元的各种源相关联的优先级来调度来自网络处理单元的处理的信息单元（或帧）的出口。 优选实施例中的优先级包括低延迟服务，最小带宽，加权公平排队以及用于在较长时间内防止用户继续超过其服务水平的系统。 本发明包括具有不同服务速率的多个日历，以允许用户选择他所期望的服务速率。 如果客户选择了高带宽的服务，客户将被包含在比客户选择较低带宽的情况下更频繁地服务的日历。