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公开(公告)号：US20240201232A1
公开(公告)日：2024-06-20
申请号：US18587508
申请日：2024-02-26
发明人： Chia-Chen Kuo , Chiting Cheng , Wei-jer Hsieh , Yangsyu Lin
IPC分类号： G01R19/165 , H02H1/00 , H02H9/02
CPC分类号： G01R19/16519 , G01R19/16538 , H02H1/0007 , H02H9/02
摘要： A power detection circuit is provided. The power detection circuit includes a comparator circuit operative to generate an output signal in response to an input signal. The output signal is configured to change from a first value to a second value in response to the input signal attaining a first threshold value. The output signal is configured to change from the second value to the first value in response to the input signal subsequently attaining a second threshold value. A current limiting circuit is connected to the comparator circuit and operative to limit a leakage current of the comparator circuit.
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公开(公告)号：US20230204634A1
公开(公告)日：2023-06-29
申请号：US18178900
申请日：2023-03-06
发明人： Chia-Chen Kuo , Chiting Cheng , Wei-jer Hsieh , Yangsyu Lin
IPC分类号： G01R19/165 , H02H1/00 , H02H9/02
CPC分类号： G01R19/16519 , G01R19/16538 , H02H1/0007 , H02H9/02
摘要： A power detection circuit is provided. The power detection circuit includes a comparator circuit operative to generate an output signal in response to an input signal. The output signal is configured to change from a first value to a second value in response to the input signal attaining a first threshold value. The output signal is configured to change from the second value to the first value in response to the input signal subsequently attaining a second threshold value. A current limiting circuit is connected to the comparator circuit and operative to limit a leakage current of the comparator circuit.
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公开(公告)号：US20220328097A1
公开(公告)日：2022-10-13
申请号：US17850354
申请日：2022-06-27
发明人： Wei-jer Hsieh , Chiting Cheng , Yangsyu Lin , Shang-Chi Wu
IPC分类号： G11C11/419 , G11C7/12 , G11C11/408 , G11C11/4096 , H01L23/522 , G11C8/08
摘要： A write assist circuit is provided. The write assist circuit includes a transistor switch coupled between a bit line voltage node of a cell array and a ground node. An invertor is operative to receive a boost signal responsive to a write enable signal. An output of the invertor is coupled to a gate of the transistor switch. The write assist circuit further includes a capacitor having a first end coupled to the bit line voltage node and a second end coupled to the gate node. The capacitor is operative to drive a bit line voltage of the bit line voltage node to a negative value from the ground voltage in response to the boost signal.
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公开(公告)号：US20220083089A1
公开(公告)日：2022-03-17
申请号：US17535206
申请日：2021-11-24
发明人： Haruki Mori , Hidehiro Fujiwara , Zhi-Hao Chang , Yangsyu Lin , Yu-Hao Hsu , Yen-Huei Chen , Hung-Jen Liao , Chiting Cheng
IPC分类号： G05F3/24 , G06F1/28 , H01L27/092 , H01L23/528 , G05F1/10
摘要： Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.
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公开(公告)号：US10559333B2
公开(公告)日：2020-02-11
申请号：US16404463
申请日：2019-05-06
发明人： Chien-Kuo Su , Cheng Hung Lee , Chiting Cheng , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yen-Huei Chen , Pankaj Aggarwal , Jhon Jhy Liaw
IPC分类号： G11C7/00 , G11C7/12 , G11C7/22 , G11C11/419
摘要： A memory macro includes a first memory cell array, first tracking circuit, first pre-charge circuit coupled to a first end of the first tracking bit line and a second pre-charge circuit coupled to a second end of the first tracking bit line. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first set of control signals, a second set of memory cells configured as a first set of pull-down cells responsive to a second set of control signals, and a first tracking bit line. The first set of pull-down cells and first set of loading cells are configured to track a memory cell of the first memory cell array. The first and second pre-charge circuit are configured to charge the first tracking bit line to a voltage level responsive to a third set of control signals.
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公开(公告)号：US10319421B2
公开(公告)日：2019-06-11
申请号：US16005121
申请日：2018-06-11
发明人： Chien-Kuo Su , Cheng Hung Lee , Chiting Cheng , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yen-Huei Chen , Pankaj Aggarwal , Jhon Jhy Liaw
IPC分类号： G11C7/00 , G11C7/12 , G11C7/22 , G11C11/419
摘要： A memory macro includes a first set of memory cells, a second set of memory cells and a set of conductive lines. The first set of memory cells is arranged in columns and rows. Each memory cell of the first set of memory cells includes a voltage supply node configured to receive a first voltage of a first supply voltage or a second voltage of a second supply voltage. The second set of memory cells includes a set of retention circuits configured to supply the second voltage of the second supply voltage to the first set of memory cells during a sleep operational mode. The set of conductive lines is coupled to the set of retention circuits and the voltage supply node of each memory cell of the first set of memory cells.
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公开(公告)号：US09997219B2
公开(公告)日：2018-06-12
申请号：US15798710
申请日：2017-10-31
发明人： Chien-Kuo Su , Cheng Hung Lee , Chiting Cheng , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yen-Huei Chen , Pankaj Aggarwal , Jhon Jhy Liaw
CPC分类号： G11C7/12 , G11C7/227 , G11C11/419
摘要： A memory macro includes a first set of memory cells, a second set of memory cells, a third set of memory cells, a set of retention circuits and a set of conductive lines. The second set of memory cells arranged in a first row arranged in a second direction. The third set of memory cells arranged in a first column arranged in a first direction. The set of retention circuits is configured to supply a second voltage value of a second supply voltage to the first set of memory cells during a sleep operational mode. The set of retention circuits is responsive to a set of control signals, and arranged in a second column arranged in the first direction. The set of conductive lines extend in the second direction, and coupled to the set of retention circuits and the voltage supply node of the first set of memory cells.
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公开(公告)号：US09263123B2
公开(公告)日：2016-02-16
申请号：US14068771
申请日：2013-10-31
IPC分类号： G11C11/00 , G11C11/419 , G11C11/413 , H01L27/11 , G11C5/14 , G11C16/30 , G11C7/02 , G11C8/08 , G11C11/418
CPC分类号： G11C11/419 , G11C5/14 , G11C7/02 , G11C8/08 , G11C11/413 , G11C11/418 , G11C16/30 , H01L27/11
摘要： A semiconductor memory device comprises an array of memory cells arranged in rows and columns, control lines coupled to the rows of memory cells for accessing the memory cells, conductive lines coupled to the rows of memory cells for powering the memory cells, and a control circuit configured to maintain non-selected conductive lines at a first voltage level and boost a selected conductive line to a second voltage level in an access operation, the second voltage level being higher than the first voltage level.
摘要翻译： 半导体存储器件包括排列成行和列的存储器单元的阵列，耦合到用于存取存储器单元的存储器单元行的控制线，耦合到用于为存储单元供电的存储单元行的导线;以及控制电路 被配置为将未选择的导线保持在第一电压电平，并且在访问操作中将所选导线升高到第二电压电平，所述第二电压电平高于所述第一电压电平。
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公开(公告)号：US11996163B2
公开(公告)日：2024-05-28
申请号：US18153464
申请日：2023-01-12
IPC分类号： G11C7/12 , G11C11/413 , G11C11/4074 , G11C11/4094 , G11C11/412 , G11C11/419
CPC分类号： G11C7/12 , G11C11/413 , G11C11/4074 , G11C11/4094 , G11C11/412 , G11C11/419
摘要： A circuit includes a memory cell column coupled to a bit line pair and a write circuit that alternately biases a first end of the bit lines toward power supply and reference voltage levels in a write operation. Each of first and second switching circuits at second ends of the bit lines includes first and second logic circuits, each including an input terminal coupled to a corresponding bit line, and first and second switching devices, each including a gate coupled to the corresponding logic circuit. The first logic circuit and switching device couple the corresponding bit line to a power supply node simultaneously with the write circuit biasing the corresponding bit line toward the power supply voltage level, and the second logic circuit and switching device couple the corresponding bit line to a reference node simultaneously with the write circuit biasing the corresponding bit line toward the reference voltage level.
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公开(公告)号：US11579648B2
公开(公告)日：2023-02-14
申请号：US17535206
申请日：2021-11-24
发明人： Haruki Mori , Hidehiro Fujiwara , Zhi-Hao Chang , Yangsyu Lin , Yu-Hao Hsu , Yen-Huei Chen , Hung-Jen Liao , Chiting Cheng
IPC分类号： G05F1/10 , G05F3/24 , G06F1/28 , H01L27/092 , H01L23/528
摘要： Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.
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