公开(公告)号：US20180041615A1

公开(公告)日：2018-02-08

申请号：US15788179

申请日：2017-10-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Patrick W. Bosshart ,  Hun-Seok Kim

IPC: H04L29/06 ,  H04L12/741

CPC classification number: H04L69/22 ,  H04L45/00 ,  H04L45/74

Abstract: A packet processing block. The block has an input for receiving data in a packet header vector, the vector comprising data representing information for a packet and a match unit for performing match operations between packet header vector data and at least one match table. Various embodiments provide advantages in connection with storing certain action or next table bits outside of the match table, or constants in the table, or by forming the match table from multiple unit match table memories.

公开(公告)号：US09584542B2

公开(公告)日：2017-02-28

申请号：US14614038

申请日：2015-02-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hun-Seok Kim ,  Anand Ganesh Dabak ,  Jing-Fei Ren ,  Manish Goel

IPC: H04L29/06 ,  H04L29/08 ,  H04L9/32 ,  H04W12/12

CPC classification number: H04L63/1466 ,  H04K1/003 ,  H04K3/25 ,  H04K3/46 ,  H04K3/65 ,  H04K3/827 ,  H04K3/86 ,  H04K2203/22 ,  H04L9/3271 ,  H04L67/12 ,  H04L2209/805 ,  H04W12/12

Abstract: An apparatus for preventing a relay attack that includes a microcontroller, a receiver, and a transmitter. The receiver is configured to receive a challenge message from a verifier. The challenge message has a challenge message frequency at a first challenge message frequency during a first time slot. The transmitter is configured to transmit a response message to the verifier. The response message has a response message frequency at a first response message frequency during the first time slot. The first response message frequency is different than the first challenge message frequency. The challenge message frequency is at a second challenge message frequency and the response message frequency is at a second response message frequency during a second time slit. The second challenge message frequency is different than the second response message frequency.

Abstract translation: 一种用于防止包括微控制器，接收器和发射器的中继攻击的装置。 接收器被配置为从验证器接收挑战消息。 挑战消息在第一时隙期间在第一挑战消息频率处具有挑战消息频率。 发送器被配置为向验证者发送响应消息。 响应消息在第一时隙期间具有在第一响应消息频率处的响应消息频率。 第一响应消息频率与第一挑战消息频率不同。 挑战消息频率处于第二挑战消息频率，并且响应消息频率在第二时间缝隙期间处于第二响应消息频率。 第二挑战消息频率与第二响应消息频率不同。

公开(公告)号：US20160330127A1

公开(公告)日：2016-11-10

申请号：US15212616

申请日：2016-07-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hun-Seok Kim ,  Patrick W. Bosshart

IPC: H04L12/851 ,  H04L12/863 ,  H04L29/06

CPC classification number: H04L47/2441 ,  H04L47/21 ,  H04L47/622 ,  H04L69/22

Abstract: An embodiment of the invention includes an Openflow switch. The Openflow switch includes Openflow ALL groups. The Openflow ALL groups include ALL group buckets. During ingress ALL group buckets are represented in ingress as a list of output ports with associated queue ID's and associated copy-counts. Each ALL group bucket is represented in egress by an egress Openflow table entry where the egress Openflow table entry matches a group ID and a bucket ID. An action entry in an ALL group bucket table entry is the set of actions in the Openflow ALL group bucket excluding an output port and queue assignment.

Abstract translation: 本发明的实施例包括一个开漏开关。 Openflow开关包括Openflow ALL组。 Openflow ALL组包括所有组桶。 在入口期间，所有组桶在入口中表示为具有相关队列ID和关联复制计数的输出端口列表。 每个ALL组桶由出口Openflow表项在出口处表示，其中出口Openflow表项与组ID和桶ID匹配。 ALL组桶表条目中的操作条目是Openflow ALL组桶中的一组操作，不包括输出端口和队列分配。

公开(公告)号：US09438266B1

公开(公告)日：2016-09-06

申请号：US15040572

申请日：2016-02-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Krishnaswamy Nagaraj ,  Manish Goel ,  Xiao Pu ,  Hun-Seok Kim

IPC: H03M1/10 ,  H03M3/00

CPC classification number: H03M3/464 ,  H03M3/38

Abstract: A direct current (“DC”) calibration reference voltage is applied at an input terminal of an N-level sigma-delta analog-to-digital converter (“ADC”). The ADC includes a current-mode DAC (“I-DAC”) operating as a feedback element. A count of logical 1s associated with each of N output levels is taken at outputs of a modulator portion of the ADC during a first mismatch measurement interval. Mismatch measurement logic subsequently transposes pairs of current sources between level selection switch matrices. Doing so causes modulator output error components resulting from mismatches between I-DAC current sources (“delta”) to appear as differential level-specific output counts. The mismatch measurement logic compares the differential counts to determine values of delta. The ADC then factors decimated modulator output counts by values of delta in order to correct for the I-DAC current source mismatch(es).

Abstract translation: 在N级Σ-Δ模数转换器（“ADC”）的输入端施加直流（“DC”）校准参考电压。 ADC包括作为反馈元件工作的电流模式DAC（“I-DAC”）。 在第一失配测量间隔期间，在ADC的调制器部分的输出处获取与N个输出电平中的每一个相关联的逻辑1的计数。 不匹配测量逻辑随后在电平选择开关矩阵之间转置电流源对。 这样做会导致由I-DAC电流源（“delta”）之间的不匹配导致的调制器输出误差分量作为差分电平特定输出计数。 不匹配测量逻辑比较差分计数以确定delta的值。 ADC然后通过delta值将衰减的调制器输出计数值除数，以校正I-DAC电流源不匹配。

公开(公告)号：US09419903B2

公开(公告)日：2016-08-16

申请号：US14072985

申请日：2013-11-06

Applicant: Texas Instruments Incorporated

Inventor： Hun-Seok Kim ,  Patrick W. Bosshart

IPC: G06F11/00 ,  H04L12/819

CPC classification number: H04L47/2441 ,  H04L47/21 ,  H04L47/622 ,  H04L69/22

Abstract: An embodiment of the invention includes an Openflow switch. The Openflow switch includes Openflow ALL groups. The Openflow ALL groups include ALL group buckets. During ingress ALL group buckets are represented in ingress as a list of output ports with associated queue ID's and associated copy-counts. Each ALL group bucket is represented in egress by an egress Openflow table entry where the egress Openflow table entry matches a group ID and a bucket ID. An action entry in an ALL group bucket table entry is the set of actions in the Openflow ALL group bucket excluding an output port and queue assignment.

Abstract translation: 本发明的实施例包括一个开漏开关。 Openflow开关包括Openflow ALL组。 Openflow ALL组包括所有组桶。 在入口期间，所有组桶在入口中表示为具有相关队列ID和关联复制计数的输出端口列表。 每个ALL组桶由出口Openflow表项在出口处表示，其中出口Openflow表项与组ID和桶ID匹配。 ALL组桶表条目中的操作条目是Openflow ALL组桶中的一组操作，不包括输出端口和队列分配。

公开(公告)号：US20160156557A1

公开(公告)日：2016-06-02

申请号：US15017770

申请日：2016-02-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Patrick William Bosshart ,  Hun-Seok Kim

IPC: H04L12/741 ,  H04L12/935

CPC classification number: H04L45/745 ,  H04L45/74 ,  H04L45/7457 ,  H04L49/3063

Abstract: An embodiment of the invention includes a memory and apparatus for packet processing in a switching network. The memory includes a plurality of words where each word includes a plurality of bits. Each word in the plurality of words is addressed by separate and distinct read address. A logic circuit performs a logical “OR” function on all the bit in all the words addressed by the separate and distinct read addresses and outputs a result.

Abstract translation: 本发明的实施例包括用于交换网络中的分组处理的存储器和装置。 存储器包括多个单词，其中每个单词包括多个位。 多个单词中的每个单词通过单独和不同的读取地址来寻址。 逻辑电路对由单独和不同读取地址寻址的所有单词中的所有位执行逻辑“或”功能，并输出结果。

公开(公告)号：US20140328180A1

公开(公告)日：2014-11-06

申请号：US14072985

申请日：2013-11-06

Applicant: Texas Instruments Incorporated

Inventor： Hun-Seok Kim ,  Patrick W. Bosshart

IPC: H04L12/819

CPC classification number: H04L47/2441 ,  H04L47/21 ,  H04L47/622 ,  H04L69/22

Abstract: An embodiment of the invention includes an Openflow switch. The Openflow switch includes Openflow ALL groups. The Openflow ALL groups include ALL group buckets. During ingress ALL group buckets are represented in ingress as a list of output ports with associated queue ID's and associated copy-counts. Each ALL group bucket is represented in egress by an egress Openflow table entry where the egress Openflow table entry matches a group ID and a bucket ID. An action entry in an ALL group bucket table entry is the set of actions in the Openflow ALL group bucket excluding an output port and queue assignment.

Abstract translation: 本发明的实施例包括一个开漏开关。 Openflow开关包括Openflow ALL组。 Openflow ALL组包括所有组桶。 在入口期间，所有组桶在入口中表示为具有相关队列ID和关联复制计数的输出端口列表。 每个ALL组桶由出口Openflow表项在出口处表示，其中出口Openflow表项与组ID和桶ID匹配。 ALL组桶表条目中的操作条目是Openflow ALL组桶中的一组操作，不包括输出端口和队列分配。

公开(公告)号：US20140244966A1

公开(公告)日：2014-08-28

申请号：US14193199

申请日：2014-02-28

Applicant: Texas Instruments Incorporated

Inventor： Patrick W. Bosshart ,  Hun-Seok Kim

IPC: G06F12/10

CPC classification number: H04L49/90

Abstract: A packet processing block. The block comprises an input for receiving data in a packet header vector, where the vector comprises data values representing information for a packet. The block also comprises circuitry for performing packet match operations in response to at least a portion of the packet header vector and data stored in a match table and circuitry for performing one or more actions in response to a match detected by the circuitry for performing packet match operations. The one or more actions comprise modifying the data values representing information for a packet. The block also comprises at least one stateful memory comprising stateful memory data values. The one or more actions includes various stateful actions for reading stateful memory, modifying data values representing information for a packet, as a function of the stateful memory data values; and storing modified stateful memory data value back into the stateful memory.

Abstract translation: 一个数据包处理块。 该块包括用于在分组报头向量中接收数据的输入，其中矢量包括表示分组的信息的数据值。 该块还包括用于响应于分组报头向量的至少一部分和存储在匹配表中的数据执行分组匹配操作的电路和用于响应于由用于执行分组匹配的电路检测到的匹配执行一个或多个动作的电路 操作。 一个或多个动作包括修改表示分组的信息的数据值。 该块还包括至少一个包含状态存储器数据值的有状态存储器。 一个或多个动作包括用于读取状态存储器的各种有状态动作，修改表示数据包的信息的数据值，作为有状态存储器数据值的函数; 并将修改的有状态存储器数据值存储回有状态存储器中。