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公开(公告)号：US20190039091A1
公开(公告)日：2019-02-07
申请号：US16053662
申请日：2018-08-02
IPC分类号： B06B1/02 , H03K17/687 , G01F1/66
摘要： In described examples, a first and second driver each include a first-rail output transistor including a first terminal coupled to a first power rail and a second-rail output transistor including a first terminal coupled to a second power rail. The first-rail output transistor of each of the first and second drivers includes a second terminal coupled to a second terminal of the second-rail output transistor of an output node of each respective first and second driver. A resistive load includes a first terminal coupled to the first-driver output node and includes a second terminal coupled to the second-driver output node. A sampling circuit generates an indication of an impedance of at least one of the output transistors of the first and second drivers.
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公开(公告)号：US09762259B1
公开(公告)日：2017-09-12
申请号：US15401957
申请日：2017-01-09
发明人： Xiao Pu , Krishnaswamy Nagaraj , Peng Cao
摘要： A notch filter in a sigma-delta modulator loop filter increases SNR by limiting in-band quantization noise around a frequency to which the notch filter is precisely tuned. A tuning mode controller isolates the notch filter from other loop filter stages. A bias voltage is applied to the notch filter, causing it to resonate. Tuning mode switches insert the notch filter into a frequency-locked loop (“FLL”) circuit as a variable frequency oscillator component of the FLL. An ADC operational mode input signal is applied to the FLL as a reference signal. A tuning control component of the FLL adjusts a tunable feedback element in the notch filter to drive the FLL error signal to zero in order to precisely tune the notch filter to the center frequency of the ADC input signal. Tuning inputs to the tunable feedback element are then latched prior to re-inserting the notch filter into the modulator.
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公开(公告)号：US09438266B1
公开(公告)日：2016-09-06
申请号：US15040572
申请日：2016-02-10
发明人： Krishnaswamy Nagaraj , Manish Goel , Xiao Pu , Hun-Seok Kim
摘要： A direct current (“DC”) calibration reference voltage is applied at an input terminal of an N-level sigma-delta analog-to-digital converter (“ADC”). The ADC includes a current-mode DAC (“I-DAC”) operating as a feedback element. A count of logical 1s associated with each of N output levels is taken at outputs of a modulator portion of the ADC during a first mismatch measurement interval. Mismatch measurement logic subsequently transposes pairs of current sources between level selection switch matrices. Doing so causes modulator output error components resulting from mismatches between I-DAC current sources (“delta”) to appear as differential level-specific output counts. The mismatch measurement logic compares the differential counts to determine values of delta. The ADC then factors decimated modulator output counts by values of delta in order to correct for the I-DAC current source mismatch(es).
摘要翻译： 在N级Σ-Δ模数转换器（“ADC”）的输入端施加直流（“DC”）校准参考电压。 ADC包括作为反馈元件工作的电流模式DAC（“I-DAC”）。 在第一失配测量间隔期间，在ADC的调制器部分的输出处获取与N个输出电平中的每一个相关联的逻辑1的计数。 不匹配测量逻辑随后在电平选择开关矩阵之间转置电流源对。 这样做会导致由I-DAC电流源（“delta”）之间的不匹配导致的调制器输出误差分量作为差分电平特定输出计数。 不匹配测量逻辑比较差分计数以确定delta的值。 ADC然后通过delta值将衰减的调制器输出计数值除数，以校正I-DAC电流源不匹配。
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公开(公告)号：US20150309525A1
公开(公告)日：2015-10-29
申请号：US14263136
申请日：2014-04-28
发明人： Xiao Pu , Krishnaswamy Nagaraj , Yue Hu
摘要： A voltage reference circuit includes a bipolar transistor and a circuit configured to measure the ratio of emitter current to base current of the bipolar transistor. The output voltage of the voltage reference circuit is compensated as a function of the measured ratio.
摘要翻译： 电压参考电路包括双极晶体管和被配置为测量双极晶体管的发射极电流与基极电流的比率的电路。 电压参考电路的输出电压作为测量比的函数进行补偿。
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5.发明申请公开(公告)号：US20150003490A1
公开(公告)日：2015-01-01
申请号：US13931799
申请日：2013-06-28
发明人： Mikel K. Ash , Xiao Pu , Joonsung Park , Krishnaswamy Nagaraj
IPC分类号： G01K15/00
CPC分类号： G01K15/005 , G01K7/01 , G01K2219/00
摘要： A temperature sensor uses a semiconductor device that has a known voltage drop characteristic that is proportional to absolute temperature (PTAT). A controllable current source is coupled to the semiconductor device and is operable to sequentially inject a bias current having a value I(bias) and fixed ratio N of I(bias) into the semiconductor device. A delta sigma analog to digital converter (ADC) has an input coupled to the semiconductor device. The delta sigma ADC is configured to sample and integrate a sequence of voltages pairs produced across the semiconductor device by repeatedly injecting an ordered sequence of selected bias currents into the semiconductor device. The ordered sequence of selected bias currents comprises M repetitions of (N×I(bias); I(bias)) and one repetition of (M×I(bias); M×N×I(bias)).
摘要翻译： 温度传感器使用具有与绝对温度（PTAT）成比例的已知电压降特性的半导体器件。 可控电流源耦合到半导体器件，并且可操作地将具有值I（偏置）和I（偏压）的固定比率N的偏置电流顺序地注入到半导体器件中。 ΔΣ模数转换器（ADC）具有耦合到半导体器件的输入。 ΔΣADC被配置为通过将选择的偏置电流的有序序列重复地注入到半导体器件中来对半导体器件产生的电压对序列进行采样和积分。 选择的偏置电流的有序序列包括（N×I（偏置）; I（偏置））和（M×I（偏置）; M×N×I（偏置））的一次重复的M次重复。
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公开(公告)号：US20140314124A1
公开(公告)日：2014-10-23
申请号：US13866301
申请日：2013-04-19
发明人： Mikel K. Ash , Krishnaswamy Nagaraj , Paul Kimelman , Steve Vu
IPC分类号： G01K7/18
CPC分类号： G01K7/01
摘要： Methods and circuits for measuring the temperature of a transistor are disclosed. An embodiment of the method includes, providing a current into a circuit, wherein the circuit is connected to the transistor. A variable resistance is connected between the base and collector of the transistor. The circuit has a first mode and a second mode, wherein the current in the first mode flows into the base of the transistor and through the resistance and the current in the second mode flows into the emitter of the transistor. Voltages in both the first mode and the second mode are measured using different resistance settings. The temperature of the transistor is calculated based on the difference between the different voltages.
摘要翻译： 公开了用于测量晶体管的温度的方法和电路。 该方法的实施例包括：向电路提供电流，其中电路连接到晶体管。 可变电阻连接在晶体管的基极和集电极之间。 电路具有第一模式和第二模式，其中第一模式中的电流流入晶体管的基极并通过电阻，并且第二模式中的电流流入晶体管的发射极。 使用不同的电阻设置来测量第一模式和第二模式中的电压。 基于不同电压之间的差值来计算晶体管的温度。
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公开(公告)号：US10784875B2
公开(公告)日：2020-09-22
申请号：US16231568
申请日：2018-12-23
发明人： Krishnaswamy Nagaraj , Wei Fu
摘要： A circuit includes a first filter, a plurality of binary-weighted capacitors, and a current source device. The circuit also includes a first plurality of switches. Each of the first plurality of switches is connected to a separate capacitor of the plurality of binary-weighted capacitors. The first plurality of switches are connected together, and the first plurality of switches are not connected to the first filter. A second plurality of switches is also included, and each of the second plurality of switches is connected to a separate capacitor of the plurality of binary-weighted capacitors and to the first filter and to a control input of the current source device. The first plurality of switches are not connected to the control input.
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8.发明授权Enhanced resolution successive-approximation register analog-to-digital converter and method 有权增强分辨率逐次逼近寄存器模数转换器和方法公开(公告)号：US09252800B1
公开(公告)日：2016-02-02
申请号：US14462916
申请日：2014-08-19
发明人： Joonsung Park , Krishnaswamy Nagaraj , Mikel Ash
摘要： An enhanced resolution successive-approximation register (SAR) analog-to-digital converter (ADC) is provided that includes a digital-to-analog converter (DAC), a comparator and enhanced resolution SAR control logic. The DAC includes analog circuitry that is configured to convert an M-bit digital input to an analog output. The comparator includes a plurality of coupling capacitors. The enhanced resolution SAR control logic is configured to generate an M-bit approximation of an input voltage and to store a residue voltage in at least one of the coupling capacitors. The residue voltage represents a difference between the input voltage and the M-bit approximation of the input voltage. The enhanced resolution SAR control logic is further configured to generate an N-bit approximation of the input voltage based on the stored residue voltage, where N>M.
摘要翻译： 提供了增强分辨率逐次逼近寄存器（SAR）模数转换器（ADC），其包括数模转换器（DAC），比较器和增强分辨率SAR控制逻辑。 DAC包括配置为将M位数字输入转换为模拟输出的模拟电路。 比较器包括多个耦合电容器。 增强分辨率SAR控制逻辑被配置为产生输入电压的M位近似值，并将剩余电压存储在至少一个耦合电容器中。 残余电压表示输入电压和输入电压的M位近似之间的差。 增强分辨率SAR控制逻辑还被配置为基于存储的残留电压来产生输入电压的N位近似，其中N> M。
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公开(公告)号：US11901910B2
公开(公告)日：2024-02-13
申请号：US17862455
申请日：2022-07-12
CPC分类号： H03M1/46
摘要： A successive approximation analog-to-digital with an input for receiving an input analog voltage, and an amplifier with a first set of electrical attributes in a sample phase and a second set of electrical attributes, differing from the first set of electrical attributes, in a conversion phase.
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公开(公告)号：US11247232B2
公开(公告)日：2022-02-15
申请号：US16053662
申请日：2018-08-02
IPC分类号： B06B1/02 , G01F1/66 , H03K17/687
摘要： In described examples, a first and second driver each include a first-rail output transistor including a first terminal coupled to a first power rail and a second-rail output transistor including a first terminal coupled to a second power rail. The first-rail output transistor of each of the first and second drivers includes a second terminal coupled to a second terminal of the second-rail output transistor of an output node of each respective first and second driver. A resistive load includes a first terminal coupled to the first-driver output node and includes a second terminal coupled to the second-driver output node. A sampling circuit generates an indication of an impedance of at least one of the output transistors of the first and second drivers.
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