公开(公告)号：US20240113155A1

公开(公告)日：2024-04-04

申请号：US18146591

申请日：2022-12-27

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Hung-Yu Chou ,  Byron Lovell Williams ,  Thomas Dyer Bonifield

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/16

CPC classification number: H01L28/10 ,  H01L21/565 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/167 ,  H01L2224/45147 ,  H01L2224/45664 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48195 ,  H01L2224/48245 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/4903 ,  H01L2224/49052 ,  H01L2224/49109 ,  H01L2924/1461 ,  H01L2924/3862

Abstract: A microelectronic device includes a galvanic isolation component having a lower isolation element over a substrate with lower bond pads connected to the lower isolation element, a dielectric plateau over the lower isolation element that does not extend to the lower bond pads, and an upper isolation element and upper bond pads over the dielectric plateau. The upper bond pads are laterally separated from the lower bond pads by an isolation distance. The microelectronic device includes high voltage wire bonds on the upper bond pads that extend upward, within 10 degrees of vertical, for a vertical distance greater than the isolation distance. The microelectronic device further includes low voltage wire bonds on the lower bond pads that have a loop height directly over a perimeter of the substrate that is less than 5 times a wire diameter of the low voltage wire bonds.

公开(公告)号：US20230282595A1

公开(公告)日：2023-09-07

申请号：US17833380

申请日：2022-06-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey Alan West ,  Elizabeth Costner Stewart

IPC: H01L23/544 ,  H01L21/78

CPC classification number: H01L23/544 ,  H01L21/78 ,  H01L2223/5446

Abstract: An integrated circuit (IC) fabrication flow including a multilevel metallization scheme wherein one or more metal layer members of a scribelane structure are formed according to one or more design constraints. A total thickness of the metal layer members of the scribelane structure along a dicing path may be limited to a threshold value to optimize dicing separation yields in a dicing operation.

公开(公告)号：US20230122868A1

公开(公告)日：2023-04-20

申请号：US18080976

申请日：2022-12-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey Alan West

IPC: H01L21/02

Abstract: A method forms a first voltage node of a high voltage component of a microelectronic device. The method also forms a plurality of dielectric layers. The method also forms a second voltage node of the high voltage component of the microelectronic device in a fourth position such that the plurality of dielectric layers is between the first voltage node and the second voltage node. During the forming a second voltage node step, a portion of a third layer in the plurality of dielectric layers, in a region outwardly positioned relative to the second voltage node, is removed to expose the second layer, in the plurality of dielectric layers, in the region.

公开(公告)号：US11532693B2

公开(公告)日：2022-12-20

申请号：US17152230

申请日：2021-01-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey Alan West ,  Byron Lovell Williams ,  Elizabeth Costner Stewart ,  Thomas Dyer Bonifeld

IPC: H01L23/552 ,  H01L23/49 ,  H01L23/522 ,  H01L49/02

Abstract: Described examples include a hybrid circuit having a component. The component has a first conductive element on a substrate having a configuration and having a first periphery and having an extension at the first periphery. The component also has a dielectric on the first conductive element. The component also has a second conductive element having the configuration on the dielectric that is proximate to and aligned with the first conductive element, and has a second periphery, the extension of the first conductive element extending past the second periphery.

公开(公告)号：US10957655B2

公开(公告)日：2021-03-23

申请号：US16291042

申请日：2019-03-04

Applicant: Texas Instruments Incorporated

Inventor： Sreeram Subramanyam Nasum ,  Kumar Anurag Shrivastava ,  Jeffrey Alan West

IPC: H01L23/552 ,  H01L23/544 ,  H01L23/00 ,  H01L27/01 ,  H01L49/02 ,  H01L21/70

Abstract: An IC includes a substrate including metal levels thereon including a top and bottom metal level with at least a transmit (Tx) circuit and receive (Rx) circuit each having ≥1 isolation capacitor and an inductor. A scribe seal around the IC includes a first portion around the Tx circuit and second portion around the Rx circuit, utilizing ≥2 of the metal levels including at least an outer metal stack. The Tx and Rx circuits are side-by-side along a direction that defines a length for the scribe seal. The outer metal stack includes a neck region between the scribe seal portions including a shorting structure including metal level(s) for shorting together the outer metal stack of the scribe seal portions. An optional routing pass-through isolated from the shorting structure includes other metal layers connecting through the neck region between node(s) within the first and second scribe seal portion.

公开(公告)号：US20210020564A1

公开(公告)日：2021-01-21

申请号：US16916748

申请日：2020-06-30

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Thomas Dyer Bonifield

IPC: H01L23/522 ,  H01L23/58

Abstract: An integrated circuit includes a semiconductor substrate and a plurality of dielectric layers over the semiconductor substrate, including a top dielectric layer. A metal plate or metal coil is located over the top dielectric layer; a metal ring is located over the top dielectric layer and substantially surrounds the metal plate or metal coil. A protective overcoat overlies the metal ring and overlies the metal plate or metal coil. A trench opening is formed through the protective overcoat, with the trench opening exposing the top dielectric layer between the metal plate/coil and the metal ring, the trench opening substantially surrounding the metal plate or metal coil.

公开(公告)号：US10707297B2

公开(公告)日：2020-07-07

申请号：US16178065

申请日：2018-11-01

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Thomas D. Bonifield ,  Byron Lovell Williams

IPC: H01L49/02 ,  H01L29/06 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L23/522 ,  H01L27/06

Abstract: A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.

公开(公告)号：US20200185336A1

公开(公告)日：2020-06-11

申请号：US16291042

申请日：2019-03-04

Applicant: Texas Instruments Incorporated

Inventor： Sreeram Subramanyam Nasum ,  Kumar Anurag Shrivastava ,  Jeffrey Alan West

IPC: H01L23/552 ,  H01L23/544 ,  H01L23/00 ,  H01L27/01 ,  H01L49/02 ,  H01L21/70

Abstract: An IC includes a substrate including metal levels thereon including a top and bottom metal level with at least a transmit (Tx) circuit and receive (Rx) circuit each having ≥1 isolation capacitor and an inductor. A scribe seal around the IC includes a first portion around the Tx circuit and second portion around the Rx circuit, utilizing ≥2 of the metal levels including at least an outer metal stack. The Tx and Rx circuits are side-by-side along a direction that defines a length for the scribe seal. The outer metal stack includes a neck region between the scribe seal portions including a shorting structure including metal level(s) for shorting together the outer metal stack of the scribe seal portions. An optional routing pass-through isolated from the shorting structure includes other metal layers connecting through the neck region between node(s) within the first and second scribe seal portion.

公开(公告)号：US10366958B2

公开(公告)日：2019-07-30

申请号：US15857234

申请日：2017-12-28

Applicant: Texas Instruments Incorporated

Inventor： Thomas Dyer Bonifield ,  Jeffrey Alan West ,  Byron Lovell Williams

IPC: B81B7/00 ,  H01L23/00 ,  H01L23/64 ,  H01L25/00 ,  H01L27/07 ,  H01L49/02 ,  H01L25/065

Abstract: A packaged multichip device includes a first IC die with an isolation capacitor utilizing a top metal layer as its top plate and a lower metal layer as its bottom plate. A second IC die has a second isolation capacitor utilizing its top metal layer as its top plate and a lower metal layer as its bottom plate. A first bondwire end is coupled to one top plate and a second bondwire end is coupled to the other top plate. The second bondwire end includes a stitch bond including a wire approach angle not normal to the top plate it is bonded to and is placed so that the stitch bond's center is positioned at least 5% further from an edge of this top plate on a bondwire crossover side compared to a distance of the stitch bond's center from the side opposite the bondwire crossover side.

公开(公告)号：US10109597B2

公开(公告)日：2018-10-23

申请号：US14536897

申请日：2014-11-10

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Thomas D. Bonifield ,  Basab Chatterjee

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/58

Abstract: An integrated circuit containing a crack deflecting scribe seal which separates an interior region of the integrated circuit from a scribeline immediately outside the integrated circuit and a method of forming the same. The crack deflecting scribe seal includes continuous metal layers and continuous contacts and continuous vias between the continuous metal layers. The continuous metal layers do not extend past the continuous contacts and continuous vias. The continuous contacts and continuous vias are recessed from edges of the underlying continuous metal layers on the scribeline side of the scribe seal, providing an angled outer surface on the scribe seal which may desirably terminate crack propagation or deflect crack propagation upward to a top surface of the scribeline or the crack deflecting scribe seal.