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    Low energy accelerator processor architecture
    21.
    发明授权
    Low energy accelerator processor architecture 有权

    公开(公告)号：US10241791B2

    公开(公告)日：2019-03-26

    申请号：US15925957

    申请日：2018-03-20

    Applicant: Texas Instruments Incorporated

    Inventor： Srinivas Lingam ,  Seok-Jun Lee ,  Johann Zipperer ,  Manish Goel

    IPC: G06F9/30 ,  G06F13/16 ,  G06F13/40 ,  G06F9/38

    Abstract: An apparatus for a low energy accelerator processor architecture is disclosed. An example arrangement is an integrated circuit that includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory; a low energy accelerator processor configured to execute instruction words received on the system bus and having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, wherein each of the execution units is configured to perform operations responsive to retrieved instruction words; and a data register file comprising a set of data registers coupled to the plurality of execution units, wherein the registers are coupled to selected ones of the plurality of execution units. Additional methods and apparatus are disclosed.

    Low Energy Accelerator Processor Architecture with Short Parallel Instruction Word and Non-Orthogonal Register Data File
    23.
    发明申请
    Low Energy Accelerator Processor Architecture with Short Parallel Instruction Word and Non-Orthogonal Register Data File 有权
    具有短并行指令字和非正交寄存器数据文件的低能量加速器处理器架构

    公开(公告)号：US20160291974A1

    公开(公告)日：2016-10-06

    申请号：US14678944

    申请日：2015-04-04

    Applicant: Texas Instruments Incorporated ,  Texas Instruments Deutschland, GMBH

    Inventor： Srinivas Lingam ,  Seok-Jun Lee ,  Johann Zipperer ,  Manish Goel

    IPC: G06F9/30 ,  G06F13/40 ,  G06F13/16

    CPC classification number: G06F9/3013 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/3877 ,  G06F9/3889 ,  G06F13/1678 ,  G06F13/4018 ,  G06F13/4022 ,  Y02D10/14 ,  Y02D10/151

    Abstract: Apparatus for a low energy accelerator processor architecture. An example arrangement is an integrated circuit that includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory ; a low energy accelerator processor configured to execute instruction words coupled to the system bus and having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to retrieved instruction words; and a non-orthogonal data register file comprising a set of data registers coupled to the plurality of execution units, the registers coupled to selected ones of the plurality of execution units. Additional methods and apparatus are disclosed.

    Abstract translation: 低能量加速器处理器架构的设备。 示例性布置是包括具有数据宽度N的系统总线的集成电路，其中N是正整数; 耦合到所述系统总线并被配置为执行从存储器检索的指令的中央处理器单元; 低能量加速器处理器，被配置为执行与所述系统总线耦合的指令字，并具有多个执行单元，所述多个执行单元包括加载存储单元，负载系数单元，乘法单元和蝶形/加法器ALU单元，每个执行单元 被配置为响应于检索到的指令字执行操作; 以及非正交数据寄存器文件，其包括耦合到所述多个执行单元的一组数据寄存器，所述寄存器耦合到所述多个执行单元中的所选择的执行单元。 公开了附加的方法和装置。

    TRACKING ENERGY CONSUMPTION USING A SEPIC-CONVERTER TECHNIQUE
    24.
    发明申请
    TRACKING ENERGY CONSUMPTION USING A SEPIC-CONVERTER TECHNIQUE 有权
    使用SEPIC转换器技术追踪能源消耗

    公开(公告)号：US20140300343A1

    公开(公告)日：2014-10-09

    申请号：US13857599

    申请日：2013-04-05

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Horst Diewald ,  Johann Zipperer ,  Peter Weber ,  Anton Brauchle

    IPC: G01R21/06

    CPC classification number: G01R21/00 ,  G01R15/002 ,  G01R21/06 ,  G01R22/10

    Abstract: The invention relates to an apparatus and method for tracking energy consumption. An energy tracking system comprises at least one switching element, at least one inductor and a control block to keep the output voltage at a pre-selected level. The switching elements are configured to apply the source of energy to the inductors. The control block compares the output voltage of the energy tracking system to a reference value and controls the switching of the switched elements in order to transfer energy for the primary voltage into a secondary voltage at the output of the energy tracking system. The electronic device further comprises an ON-time and OFF-time generator and an accumulator wherein the control block is coupled to receive a signal from the ON-time and OFF-time generator and generates switching signals for the at least one switching element in the form of ON-time pulses with a constant width ON-time.

    Abstract translation: 本发明涉及一种跟踪能量消耗的装置和方法。 能量跟踪系统包括至少一个开关元件，至少一个电感器和控制块，以将输出电压保持在预选的电平。 开关元件被配置为将电源施加到电感器。 控制块将能量跟踪系统的输出电压与参考值进行比较，并控制开关元件的切换，以将能量跟踪系统的输出端的一次电压的能量传递到二次电压。 电子设备还包括接通时间和关断时间发生器和累加器，其中控制块被耦合以从接通时间和断开时间发生器接收信号，并且生成用于所述至少一个开关元件的切换信号 具有恒定宽度导通时间的导通时间脉冲的形式。

    TRACKING ENERGY CONSUMPTION USING A BOOST TECHNIQUE
    25.
    发明申请
    TRACKING ENERGY CONSUMPTION USING A BOOST TECHNIQUE 有权
    使用增压技术追踪能源消耗

    公开(公告)号：US20140300342A1

    公开(公告)日：2014-10-09

    申请号：US13857568

    申请日：2013-04-05

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Horst Diewald ,  Johann Zipperer ,  Peter Weber ,  Anton Brauchle

    IPC: G01R11/36

    CPC classification number: G01R15/18 ,  G01R22/10

    Abstract: The invention relates to an apparatus and method for tracking energy consumption. An energy tracking system comprises at least one switching element, at least one inductor and a control block to keep the output voltage at a pre-selected level. The switching elements are configured to apply the source of energy to the inductors. The control block compares the output voltage of the energy tracking system to a reference value and controls the switching of the switched elements in order to transfer energy for the primary voltage into a secondary voltage at the output of the energy tracking system. The electronic device further comprises an ON-time and OFF-time generator and an accumulator wherein the control block is coupled to receive a signal from the ON-time and OFF-time generator and generates switching signals for the at least one switching element in the form of ON-time pulses with a constant width ON-time.

    Abstract translation: 本发明涉及一种跟踪能量消耗的装置和方法。 能量跟踪系统包括至少一个开关元件，至少一个电感器和控制块，以将输出电压保持在预选的电平。 开关元件被配置为将电源施加到电感器。 控制块将能量跟踪系统的输出电压与参考值进行比较，并控制开关元件的切换，以将能量跟踪系统的输出端的一次电压的能量传递到二次电压。 电子设备还包括接通时间和关断时间发生器和累加器，其中控制块被耦合以从接通时间和断开时间发生器接收信号，并且生成用于所述至少一个开关元件的切换信号 具有恒定宽度导通时间的导通时间脉冲的形式。

    PROCESSOR WITH EXECUTION UNIT INTEROPERATION
    26.
    发明申请
    PROCESSOR WITH EXECUTION UNIT INTEROPERATION 审中-公开
    处理器与执行单位交互

    公开(公告)号：US20140089645A1

    公开(公告)日：2014-03-27

    申请号：US13628373

    申请日：2012-09-27

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Horst Diewald ,  Johann Zipperer

    IPC: G06F9/30

    CPC classification number: G06F9/3885 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/3012 ,  G06F9/3828

    Abstract: A processor includes a plurality of execution units. Each of the execution units includes processing logic configured to process data, and registers accessible by the processing logic. At least one of the execution units is configured to execute a first instruction that causes the at least one execution unit to: route a value from a first register of the registers of one of the execution units to the processing logic of one of the execution units, to process the value in the processing logic to generate a result, and to store the result in a second register of the registers of one of the execution units. At least one of the first register, the second register, and the processing logic are located in a different one of the execution units from the at least one of the execution units.

    Abstract translation: 处理器包括多个执行单元。 每个执行单元包括被配置为处理数据的处理逻辑和由处理逻辑可访问的寄存器。 所述执行单元中的至少一个被配置为执行使所述至少一个执行单元执行以下操作的第一指令：将来自所述执行单元之一的寄存器的第一寄存器的值路由到所述执行单元之一的处理逻辑 处理处理逻辑中的值以产生结果，并将结果存储在执行单元之一的寄存器的第二寄存器中。 第一寄存器，第二寄存器和处理逻辑中的至少一个位于与执行单元中的至少一个执行单元不同的执行单元中。

    Monitoring transitions of a circuit
    28.
    发明授权
    Monitoring transitions of a circuit 有权

    公开(公告)号：US11755342B2

    公开(公告)日：2023-09-12

    申请号：US17123407

    申请日：2020-12-16

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Ronald Nerlich ,  Mark Jung ,  Johann Zipperer ,  Dietmar Walther

    IPC: G05B1/03 ,  G06F9/448 ,  G06F8/34 ,  G05B19/045

    CPC classification number: G06F9/4498 ,  G05B19/045 ,  G06F8/34

    Abstract: A circuit includes a guard trigger circuit that includes a first input node adapted to be coupled to a first state signal, a second input node adapted to be coupled to a second state signal and an output node. The circuit also includes a reset synchronizer circuit that includes an input node coupled to the output node of the guard trigger circuit, a clock node adapted to be coupled to a clock signal and an output node. The circuit further includes a timeout circuit including an input node coupled to the output node of the reset synchronizer circuit, a clock node adapted to be coupled to the clock signal and an output node. The circuit still further includes a reset requestor circuit that includes a first input node coupled to the output node of the guard trigger circuit, a second node coupled to the output node of the timeout circuit.

    PROCESSOR WITH VARIABLE PRE-FETCH THRESHOLD
    30.
    发明申请
    PROCESSOR WITH VARIABLE PRE-FETCH THRESHOLD 有权

    公开(公告)号：US20220100522A1

    公开(公告)日：2022-03-31

    申请号：US17550572

    申请日：2021-12-14

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Christian Wiencke ,  Johann Zipperer

    IPC: G06F9/38 ,  G06F9/30

    Abstract: A method and apparatus for controlling pre-fetching in a processor. A processor includes an execution pipeline and an instruction pre-fetch unit. The execution pipeline is configured to execute instructions. The instruction pre-fetch unit is coupled to the execution pipeline. The instruction pre-fetch unit includes instruction storage to store pre-fetched instructions, and pre-fetch control logic. The pre-fetch control logic is configured to fetch instructions from memory and store the fetched instructions in the instruction storage. The pre-fetch control logic is also configured to provide instructions stored in the instruction storage to the execution pipeline for execution. The pre-fetch control logic is further configured set a maximum number of instruction words to be pre-fetched for execution subsequent to execution of an instruction currently being executed in the execution pipeline. The maximum number is based on a value contained in a pre-fetch threshold field of an instruction executed in the execution pipeline.

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