公开(公告)号：US11282770B2

公开(公告)日：2022-03-22

申请号：US17039080

申请日：2020-09-30

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Nazila Dadvand ,  Sreenivasan Koduri

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  C25D3/38

Abstract: A leadless packaged semiconductor device includes a metal substrate having at least a first through-hole aperture having a first outer ring and a plurality of cuts through the metal substrate to define spaced apart metal pads on at least two sides of the first through-hole aperture. A semiconductor die that has a back side metal (BSM) layer on its bottom side and a top side with circuitry coupled to bond pads is mounted top side up on the first outer ring. A metal die attach layer is directly between the BSM layer and walls of the metal substrate bounding the first through-hole aperture that provides a die attachment that fills a bottom portion of the first through-hole aperture. Bond wires are between metal pads and the bond pads. A mold compound is also provided including between adjacent ones of the metal pads.

公开(公告)号：US11145598B2

公开(公告)日：2021-10-12

申请号：US16236042

申请日：2018-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook ,  Nazila Dadvand ,  Archana Venugopal ,  Luigi Colombo

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

Abstract: An interconnect structure for a semiconductor device includes a plurality of unit cells. Each unit cell is formed of interconnected conducting segments. The plurality of unit cells forms a conducting lattice.

公开(公告)号：US11127515B2

公开(公告)日：2021-09-21

申请号：US16854839

申请日：2020-04-21

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L23/00 ,  H01B13/00 ,  H01B1/02

Abstract: A nanostructure barrier for copper wire bonding includes metal grains and inter-grain metal between the metal grains. The nanostructure barrier includes a first metal selected from nickel or cobalt, and a second metal selected from tungsten or molybdenum. A concentration of the second metal is higher in the inter-grain metal than in the metal grains. The nanostructure barrier may be on a copper core wire to provide a coated bond wire. The nanostructure barrier may be on a bond pad to form a coated bond pad. A method of plating the nanostructure barrier using reverse pulse plating is disclosed. A wire bonding method using the coated bond wire is disclosed.

公开(公告)号：US20210098331A1

公开(公告)日：2021-04-01

申请号：US16586720

申请日：2019-09-27

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Nazila Dadvand ,  Daniel Lee Revier ,  Archana Venugopal

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/285

Abstract: In described examples, a circuit (e.g., an integrated circuit) includes a semiconductor substrate that includes a frontside surface and a backside surface. A circuit element is included at the frontside surface. An optional electrical insulator layer can be included adjacent to the backside surface. A distributor layer is included adjacent to the backside surface. In some examples, the distributor layer includes a distributor material that includes a matrix of cohered nanoparticles and metallic particles embedded by the cohered nanoparticles.

公开(公告)号：US20210013133A1

公开(公告)日：2021-01-14

申请号：US17039080

申请日：2020-09-30

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Nazila Dadvand ,  Sreenivasan Koduri

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  C25D3/38

Abstract: A leadless packaged semiconductor device includes a metal substrate having at least a first through-hole aperture having a first outer ring and a plurality of cuts through the metal substrate to define spaced apart metal pads on at least two sides of the first through-hole aperture. A semiconductor die that has a back side metal (BSM) layer on its bottom side and a top side with circuitry coupled to bond pads is mounted top side up on the first outer ring. A metal die attach layer is directly between the BSM layer and walls of the metal substrate bounding the first through-hole aperture that provides a die attachment that fills a bottom portion of the first through-hole aperture. Bond wires are between metal pads and the bond pads. A mold compound is also provided including between adjacent ones of the metal pads.

公开(公告)号：US20200286837A1

公开(公告)日：2020-09-10

申请号：US16292878

申请日：2019-03-05

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: An integrated circuit (IC) includes a substrate with a semiconductor surface layer including circuitry configured for realizing at least one circuit function including a plurality of transistors, including at least one dielectric layer having a first and a second through-via over the plurality of transistors. The through-vias include a first top level via and at least a second top level via lateral to the first top level via. A composite layer includes copper (Cu), a first metal including zinc, and a second metal, wherein the composite layer is on a barrier layer that is on the first top level via and on the second top level. A plurality of Cu traces includes a first Cu top metal trace on the composite layer contacting the first top level via and a second Cu metal trace on the composite layer contacting the second top level via.

公开(公告)号：US20200248329A1

公开(公告)日：2020-08-06

申请号：US16268047

申请日：2019-02-05

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand

IPC: C25D3/38 ,  C25D5/02 ,  C25D5/10 ,  C25D5/50 ,  C25D7/12 ,  H01L23/00

Abstract: A microelectronic device is formed by forming a seed layer that contains primarily zinc. A plating mask is formed over the seed layer, and a copper strike layer is formed on the seed layer using a neutral pH copper plating bath. A main copper layer is formed on the copper strike layer by plating copper on the copper strike layer. The plating mask is subsequently removed. The main copper layer, the copper strike layer, and the seed layer are heated to diffuse copper and zinc, and form a brass layer under the main copper layer, consuming the seed layer between the main copper layer and the substrate. Remaining portions of the seed layer are removed by a wet etch process. The main copper layer and the underlying brass layer provide a conductor structure.

公开(公告)号：US20200219801A1

公开(公告)日：2020-07-09

申请号：US16239400

申请日：2019-01-03

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand

IPC: H01L23/495 ,  H01L23/532 ,  H05K3/34 ,  H01L23/00 ,  H01L23/28

Abstract: A device and method for fabrication thereof is provided which results in corrosion resistance of metal flanges of a semiconductor package, such as a quad flat no-lead package (QFN). Using metal electroplating (such as electroplating of nickel (Ni) or nickel alloys on copper flanges of the QFN package), corrosion resistance for the flanges is provided using a process that allows an electric current to reach the entire backside of a substrate to permit electroplating. In addition, the method may be used to directly connect a semiconductor die to the metal substrate of the package.

公开(公告)号：US20250087563A1

公开(公告)日：2025-03-13

申请号：US18958152

申请日：2024-11-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand ,  Bernardo Gallegos

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a pad and leads, the pad and leads including a base metal predominantly including copper, a first plated metal layer predominantly including nickel in contact with the base metal, and a second plated metal layer predominantly including silver in contact with the first plated metal layer. The first plated metal layer has a first plated metal layer thickness of 0.1 to 5 microns, and the second plated metal layer has a second plated metal layer thickness of 0.2 to 5 microns. The semiconductor package further includes an adhesion promotion coating predominantly including silver oxide in contact with the second plated metal layer opposite the first plated metal layer, a semiconductor die mounted on the pad, a wire bond extending between the semiconductor die and a lead of the leads, and a mold compound covering the semiconductor die and the wire bond.

公开(公告)号：US20250066526A1

公开(公告)日：2025-02-27

申请号：US18942875

申请日：2024-11-11

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo

IPC: C08F292/00 ,  C08F8/42 ,  C08J5/00 ,  C08K3/04 ,  C08K3/08 ,  C08K7/00 ,  C08L25/06 ,  C08L33/12 ,  G03F1/78

Abstract: A method of forming a composite material includes photo-initiating a polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice. Unpolymerized monomer is removed from the polymer microlattice. The polymer microlattice is coated with a metal. The metal-coated polymer microlattice is dispersed in a polymer matrix.