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公开(公告)号：US11973423B2
公开(公告)日：2024-04-30
申请号：US17238979
申请日：2021-04-23
Applicant: Texas Instruments Incorporated
Inventor： Kuang-Yao Cheng , Muthusubramanian Venkateswaran , Dattatreya Baragur Suryanarayana , Preetam Charan Anand Tadeparthy
CPC classification number: H02M3/158 , H02M1/0061 , H02M1/0016 , H02M1/0067 , H02M1/0077 , H02M3/1586
Abstract: A system includes a load and a switching converter coupled to the load. The switching converter includes at least one switching module and an output inductor coupled to a switch node of each switching module. The switching converter also includes a controller coupled to each switching module, where the controller is configured to adjust a pulse clock rate and a switch on-time for each switching module. The controller comprises a pulse truncation circuit configured to detect a voltage overshoot condition and to truncate an active switch on-time pulse in response to the detected voltage overshoot condition.
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公开(公告)号：US20230035151A1
公开(公告)日：2023-02-02
申请号：US17390539
申请日：2021-07-30
Applicant: Texas Instruments Incorporated
Inventor： Ammineni Balaji , Preetam Charan Anand Tadeparthy , Naman Bafna , Sreelakshmi Suresh , Cheng Wei Chen
Abstract: Described embodiments include a voltage regulator circuit comprising a first comparator having a first comparator input coupled to a waveform input source, a second comparator input coupled to an output voltage terminal and a first comparator output. There is a second comparator having third and fourth comparator inputs and a second comparator output, the third comparator input coupled to a voltage source configured to provide a voltage representing a current limit, and the fourth comparator input coupled to the output voltage terminal. There is also a state machine having a first state machine input coupled to the first comparator output, a second state machine input coupled to the second comparator output and a state machine output, wherein a state of the state machine is determined by the first and second comparator outputs, and the state machine output provides a PWM signal responsive to the state of the state machine.
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公开(公告)号：US11569744B2
公开(公告)日：2023-01-31
申请号：US17152223
申请日：2021-01-19
Applicant: Texas Instruments Incorporated
Inventor： Scott Edward Ragona , Rengang Chen , Preetam Charan Anand Tadeparthy , Evan Michael Reutzel
Abstract: A converter stage having a control pin, an input voltage pin, an output pin, a ground pin, a high-side switch coupled between the input voltage pin and the output pin, a low-side switch coupled between the output pin and the ground pin, a current sensor configured to detect a current at the output pin, and control logic coupled to the control pin and the current sensor. The control logic is configured to control switching of the high-side and the low-side switches in continuous conduction mode, discontinuous conduction mode, and body braking control for the converter stage in response to a first signal received via the control line and a second signal received from the current sensor. A driver controls switching, based on the detected current and sequential event tracking, between an on state and an off state.
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公开(公告)号：US10892771B1
公开(公告)日：2021-01-12
申请号：US16582243
申请日：2019-09-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rohit Narula , Preetam Charan Anand Tadeparthy , Mayank Jain
Abstract: An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC) having a resistor network. The resistor network includes a first and second segments. The first segment includes a first switch coupled between a first supply voltage node and a first set of resistors. The second segment includes a second switch coupled between the first supply voltage node and a second set of resistors. The first segment includes a third switch coupled in series with a second resistor. The series-combination of the third switch and second resistor coupled in parallel with at least one resistor of the first set of resistors. The second segment includes a fourth switch coupled in series with a third resistor. The series-combination of the fourth switch and third resistor is coupled in parallel with at least one resistor of the second set of resistors.
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公开(公告)号：US10666279B1
公开(公告)日：2020-05-26
申请号：US16287711
申请日：2019-02-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Matthew John Ascher Schurmann , Mayank Jain , Wenkai Wu , Preetam Charan Anand Tadeparthy , Kuang-Yao Cheng
IPC: H03M1/12 , H03M1/10 , H03M1/16 , H03K19/173
Abstract: A circuit includes a phase control logic, an analog-to-digital converter (ADC), and digital logic. The phase control logic is configured to couple to a plurality of power phases of a multi-phase power supply. The digital logic is configured to couple to the phase control logic and the ADC, to receive an instruction to operate in a self-calibration mode of operation, receive a first message including a value associated with a calibrated load configured to couple to the plurality of power phases, perform a self-calibration sub-routine for each power phase of the plurality of power phases based at least partially on the received instruction, the received first message, and a signal received from the ADC, and receive a second message instructing the digital logic to store a result of the self-calibration in a memory of the circuit.
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Patent Agency Ranking
公开(公告)号：US11955879B2
公开(公告)日：2024-04-09
申请号：US17137446
申请日：2020-12-30
Applicant: Texas Instruments Incorporated
Inventor： Venkatesh Wadeyar , Vikas Lakhanpal , Preetam Charan Anand Tadeparthy
Abstract: In described examples, a controller includes a converter. The converter generates a first signal responsive to an input signal. A summing block is coupled to the converter. The summing block receives the first signal and generates a second signal. A limiter is coupled to the summing block and generates a third signal responsive to the second signal and a code signal. A logic block generates a target signal responsive to the third signal. The third signal transitions to an intermediate level at a first slew rate and the third signal transitions from the intermediate level to the target signal at a second slew rate.
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公开(公告)号：US11888393B2
公开(公告)日：2024-01-30
申请号：US17537595
申请日：2021-11-30
Applicant: Texas Instruments Incorporated
Inventor： Muthusubramanian Venkateswaran , Rohit Narula , Preetam Charan Anand Tadeparthy , Matthew John Ascher Schurmann , Rajesh Venugopal
CPC classification number: H02M3/155 , H02M1/08 , H02M1/32 , H02M1/36 , H02M3/1586
Abstract: A multiphase controller includes an integrator enable terminal, a pulse width modulator, an error integrator, an open drain driver, and an integrator enable circuit. The integrator enable terminal is adapted to be coupled to the integrator enable terminal of a different instance of the multiphase controller. The pulse width modulator is configured to modulate a power stage. The error integrator is configured to control the pulse width modulator. The open drain driver is coupled to the integrator enable circuit. The integrator enable circuit is coupled to the pulse width modulator, the error integrator, the open drain driver, and the integrator enable terminal. The integrator enable circuit is configured to activate the open drain driver responsive to generation of a power stage control pulse by the pulse width modulator, and activate the error integrator responsive to a logic low signal at the integrator enable terminal.
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公开(公告)号：US11799427B2
公开(公告)日：2023-10-24
申请号：US17514087
申请日：2021-10-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
CPC classification number: H03F3/04 , H02M3/155 , H03F1/086 , H03F3/45192 , H03F3/505 , H03F2203/45124
Abstract: An amplifier includes a first stage and a second stage. The first stage is configured to amplify a received signal. The second stage is coupled to the first stage. The second stage includes a source follower and a compensation network. The source follower includes an input and an output. The compensation network is coupled to the input of the source follower and the output of the source follower. The compensation network is configured to modify a magnitude and phase response of the first stage based on a load capacitance coupled to the output of the source follower.
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公开(公告)号：US11757358B2
公开(公告)日：2023-09-12
申请号：US17490671
申请日：2021-09-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Naman Bafna , Preetam Charan Anand Tadeparthy , Ammineni Balaji , Sreelakshmi Suresh , Mayank Jain
CPC classification number: H02M3/157 , H02M1/0009 , H02M1/0845
Abstract: In an example, a method includes storing a pending PWM pulse for a switching voltage regulator. The method also includes determining a switching voltage regulator is operating in a current limit mode, where an inductor current is above a current limit threshold. The method includes providing a predetermined number of PWM pulses in the current limit mode. The method also includes, responsive to providing the predetermined number of PWM pulses, ceasing storage of pending PWM pulses for the switching voltage regulator.
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公开(公告)号：US11711016B2
公开(公告)日：2023-07-25
申请号：US17489782
申请日：2021-09-30
Applicant: Texas Instruments Incorporated
Inventor： Naman Bafna , Preetam Charan Anand Tadeparthy , Ammineni Balaji , Sreelakshmi Suresh
CPC classification number: H02M3/158 , H02M1/0025
Abstract: In described examples of a system having a proportional-integral control module, an error signal is produced that is indicative of a difference between a reference signal and an output signal. An integral control signal is produced by integrating the error signal using an integrator time constant value. During a steady state condition, a first integrator time constant value is used. When an undershoot in the output signal is detected, the integrator time constant value is increased to a second time constant value that is larger than the first integrator time constant value during the undershoot condition. The integrator time constant value is reduced to a third integrator time constant value that is less than the first integrator time constant value during a period following the undershoot condition.
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