公开(公告)号：US09331734B2

公开(公告)日：2016-05-03

申请号：US14740961

申请日：2015-06-16

Applicant: Texas Instruments Incorporated ,  TEXAS INSTRUMENTS DEUTSCHLAND GmbH

Inventor： Sudipto Chakraborty ,  David LeDeaut ,  Josef Einzinger ,  Jens Graul ,  Vadim Valerievich Ivanov

IPC: H04B1/40 ,  H04B1/401 ,  H04B1/04 ,  H04B1/18

CPC classification number: H04B1/401 ,  H03F3/24 ,  H04B1/0458 ,  H04B1/18 ,  H04B2001/0408

Abstract: A system on a chip (SoC) includes a transceiver comprising a transmitter and a receiver, wherein at least one of the transmitter and receiver has a configurable portion that can be configured to operate in a single ended mode and in a differential mode. Two interface pins are provided for coupling the transceiver to an antenna via a matching network, wherein the two interface pins are shareably coupled to the transmitter and to the receiver. A tunable capacitor is coupled to differential signal lines of the configurable portion, wherein the tunable capacitor is configured to be tuned to optimize impedance matching of the configurable portion for each mode of operation.

Abstract translation: 芯片上的系统（SoC）包括收发器，其包括发射器和接收器，其中发射器和接收器中的至少一个具有可配置部分，其可被配置为以单端模式和差分模式操作。 提供两个接口引脚用于通过匹配网络将收发器耦合到天线，其中两个接口引脚可共享地耦合到发射器和接收器。 可调电容器耦合到可配置部分的差分信号线，其中可调谐电容器被配置为调整以优化每个操作模式的可配置部分的阻抗匹配。

公开(公告)号：US20240036076A1

公开(公告)日：2024-02-01

申请号：US17874667

申请日：2022-07-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vadim Valerievich Ivanov ,  Srinivas Pulijala ,  Piyush Kaslikar

IPC: G01R15/14 ,  G01R19/252

CPC classification number: G01R15/146 ,  G01R19/252 ,  H02M1/0009

Abstract: A current measurement and control circuit may comprise a shunt resistor coupled between supply and output nodes; a first resistor coupled to the supply node; a second resistor coupled to ground; and a transconductance amplifier having an input coupled to the first resistor to define a compensation node and another input coupled to the output node. The circuit may also include a first transistor having a first current terminal coupled to the compensation node and a second current terminal coupled to the second resistor to define a measurement node; and a second transistor having a first current terminal coupled to ground and a second current terminal coupled to the output node. The circuit may also include an ADC having an analog input coupled to the measurement node; an IDAC having an analog output coupled to the compensation node; and switches to set the circuit in a measurement or a compensation mode.

公开(公告)号：US11881825B2

公开(公告)日：2024-01-23

申请号：US17136073

申请日：2020-12-29

Applicant: Texas Instruments Incorporated

Inventor： Vadim Valerievich Ivanov ,  Munaf Hussain Shaik ,  Srinivas Kumar Pulijala ,  Patrick Forster ,  Jerry Lee Doorenbos

IPC: H03F3/45 ,  H03M1/66 ,  H03M1/38

CPC classification number: H03F3/45475 ,  H03M1/38 ,  H03M1/66 ,  H03F2200/375

Abstract: Disclosed is a system that comprises an operational amplifier with adjustable operational parameters and a trimming module. The trimming module can adjust the operational parameters of the op-amp based on a memory value to compensate for an offset voltage of the op-amp. The trimming module can comprise successive approximation register (SAR) logic that controls the memory value. The SAR logic can be configured to detect a given memory value that causes an output voltage of the op-amp to be within a predetermined voltage interval when applying a predetermined common mode voltage to inverting and non-inverting inputs of the op-amp.

公开(公告)号：US11876496B2

公开(公告)日：2024-01-16

申请号：US17386979

申请日：2021-07-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vadim Valerievich Ivanov ,  Srinivas Kumar Pulijala

IPC: H03F3/45 ,  H03F1/52

CPC classification number: H03F3/45179 ,  H03F1/52 ,  H03F2200/426

Abstract: Differential input circuits employ protection transistors and feedback paths to limit the differential voltage applied to input transistors. In an example arrangement, a differential input voltage is applied to terminals of the protection transistors, and current paths couple the respective protection transistors to control terminals of the input transistors, respectively. A control terminal drive voltage source is coupled to the control terminals of the input protection transistors to control the drive voltage applied to those terminals. Feedback paths, one for each of the input transistors, control voltages applied to the control terminals of the input transistors, maintaining the input differential voltage at a relatively low level and defined by the product of a specified current value and a specified resistance value.

公开(公告)号：US11009900B2

公开(公告)日：2021-05-18

申请号：US15400976

申请日：2017-01-07

Applicant: Texas Instruments Incorporated

Inventor： Vadim Valerievich Ivanov ,  Sahana Sriraj

IPC: G05F1/575

Abstract: Low dropout regulators (LDOs) are disclosed herein. An example of an LDO includes an error amplifier having a first input and a second input, wherein the first input is for coupling to an output of the LDO and the second input for coupling to a reference voltage. The error amplifier has an output with a voltage that is proportional to the difference between the output voltage and the reference voltage. A second amplifier is coupled between the error amplifier and the output of the LDO. A gain boost amplifier is coupled between the error amplifier and the second amplifier. The gain boost amplifier increases DC gain of the LDO in response to a load step on the output.

公开(公告)号：US10931247B2

公开(公告)日：2021-02-23

申请号：US16357572

申请日：2019-03-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vadim Valerievich Ivanov ,  Bharath Karthik Vasan ,  Piyush Kaslikar ,  Srinivas K. Pulijala

IPC: H03F1/02 ,  H03F3/387 ,  H03F3/19

Abstract: A chopper amplifier circuit includes a first amplifier path, a second amplifier path, and a third amplifier path. The first amplifier path includes chopper circuitry configured to modulate an input signal and an offset voltage at a chopping frequency, and ripple reduction circuitry configured to attenuate the chopping frequency in a signal in the first amplifier path. The second amplifier path includes a feedforward gain stage, and is configured to apply higher gain to intermediate signal frequencies than is applied in the first amplifier path. The third amplifier path includes a feedforward gain stage, and is configured to apply higher gain to high signal frequencies than is applied in the first amplifier path and the second amplifier path. The intermediate signal frequencies are lower than the high signal frequencies.

公开(公告)号：US10461707B2

公开(公告)日：2019-10-29

申请号：US15912642

申请日：2018-03-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vadim Valerievich Ivanov

IPC: H03F3/45 ,  H03F1/02 ,  H03F1/22

Abstract: An amplifier includes an input stage, a folded cascode stage, and a class AB output stage. The folded cascode stage is coupled to the input stage. The class AB output stage is coupled to the folded cascode stage. The class AB output stage includes a high-side output transistor, a low-side output transistor, and a high-side feedback circuit that is coupled to the high-side output transistor. The high-side feedback circuit includes a high-side sense transistor and a high-side feedback transistor. The high-side sense transistor includes a control terminal that is coupled to a control terminal of the high-side output transistor. The high-side feedback transistor is coupled to an output of the high-side sense transistor and to the folded cascode stage. A first output of the folded cascode stage is coupled to the control terminal of the high-side sense transistor and to the control terminal of the high-side output transistor.

公开(公告)号：US09054657B2

公开(公告)日：2015-06-09

申请号：US14040856

申请日：2013-09-30

Applicant: Texas Instruments Incorporated

Inventor： Vaibhav Kumar ,  Vadim Valerievich Ivanov

IPC: H03F3/45

CPC classification number: H03F3/45179 ,  H03F3/45 ,  H03F3/45183 ,  H03F3/45475 ,  H03F2203/45248 ,  H03F2203/45344 ,  H03F2203/45511 ,  H03F2203/45512

Abstract: In an amplifier, a first stage receives a differential input voltage, which is formed by first and second input voltages, and outputs a first differential current in response thereto on first and second lines having respective first and second line voltages. A second stage receives the first and second line voltages and outputs a second differential current in response thereto on third and fourth lines having respective third and fourth line voltages. A third stage receives the third and fourth line voltages and outputs an output voltage in response thereto. A slew boost circuit detects a slew condition, in which a threshold difference arises between the first and second input voltages, and outputs a slew current in response thereto for maintaining a slew rate of the output voltage during the slew condition. The first stage includes circuits for reducing a variable difference between the first and second line voltages.

Abstract translation: 在放大器中，第一级接收由第一和第二输入电压形成的差分输入电压，并且在具有相应的第一和第二线电压的第一和第二线上响应于此输出第一差分电流。 第二级接收第一和第二线电压，并在具有相应的第三和第四线电压的第三和第四线上响应于此输出第二差分电流。 第三级接收第三和第四线电压并输出响应于此的输出电压。 回转升压电路检测在第一和第二输入电压之间出现阈值差的转换条件，并且响应于此产生一个回转电流，以保持在转换条件期间输出电压的转换速率。 第一级包括用于减小第一和第二线电压之间的可变差的电路。

公开(公告)号：US20150028949A1

公开(公告)日：2015-01-29

申请号：US13950643

申请日：2013-07-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Graham Brantley ,  Vadim Valerievich Ivanov

IPC: H03F3/45 ,  H03F1/02

CPC classification number: H03F3/45376 ,  H03F2203/45568 ,  H03F2203/45571

Abstract: A differential input circuit (FIG. 3A) is disclosed. The circuit includes a first input terminal (drain of 310) and a second input terminal (drain of 312). A first input transistor (310) has a first control terminal and has a current path coupled to the first input terminal. A second input transistor (312) has a second control terminal and has a current path coupled to the second input terminal. A third transistor (306) has a third control terminal and has a current path between a first differential input terminal (Vin+) and the first control terminal. A fourth transistor (308) has a fourth control terminal and has a current path between a second differential input terminal (Vin−) and the second control terminal.

Abstract translation: 公开了一种差分输入电路（图3A）。 电路包括第一输入端（310的漏极）和第二输入端（312的漏极）。 第一输入晶体管（310）具有第一控制端并具有耦合到第一输入端的电流通路。 第二输入晶体管（312）具有第二控制端子并且具有耦合到第二输入端子的电流通路。 第三晶体管（306）具有第三控制端子，并且在第一差分输入端（Vin +）和第一控制端之间具有电流路径。 第四晶体管（308）具有第四控制端子，并且在第二差分输入端子（Vin-）和第二控制端子之间具有电流路径。

公开(公告)号：US08836377B1

公开(公告)日：2014-09-16

申请号：US13869634

申请日：2013-04-24

Applicant: Texas Instruments Incorporated

Inventor： Vadim Valerievich Ivanov ,  Ravi Balasingam ,  Ritu Shree

IPC: H03K5/153

CPC classification number: H03K3/01 ,  G01R19/16542 ,  G01R19/16576 ,  G06F1/1626 ,  G06F1/28 ,  H02H3/207

Abstract: A power supervisor circuit is provided. The circuit includes a first sample circuit that periodically samples a first reference voltage derived from a high output rail of a voltage source and generates a first sampled output voltage. The circuit includes second sample circuit that periodically samples a second reference voltage associated with a low output rail of the voltage source and generates a second sampled output voltage. A voltage supervisor in the circuit generates a trip point signal when a combination of the first and second sampled output voltage crosses a predetermined threshold indicating that the voltage source output voltage has fallen below a desired output voltage.

Abstract translation: 提供电源管理电路。 电路包括第一采样电路，其周期性地对从电压源的高输出轨导出的第一参考电压进行采样，并产生第一采样输出电压。 电路包括第二采样电路，周期性地对与电压源的低输出轨相关联的第二参考电压进行采样，并产生第二采样输出电压。 当第一和第二采样输出电压的组合跨过预定阈值，指示电压源输出电压已经低于期望输出电压时，电路中的电压监控器产生跳变点信号。