公开(公告)号：US20230352850A1

公开(公告)日：2023-11-02

申请号：US18309720

申请日：2023-04-28

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Murugan ,  Harshpreet Singh Phull Bakshi ,  Sylvester Ankamah-Kusi ,  Juan Herbsommer ,  Aditya Nitin Jogalekar

IPC: H01Q21/00 ,  H01Q1/22

CPC classification number: H01Q21/005 ,  H01Q1/2283

Abstract: An example microelectronic device package includes: a multilayer package substrate including a slotted waveguide antenna and having routing conductors, the multilayer package substrate having a device side surface and an opposing board side surface; a semiconductor die mounted to the device side surface of the multilayer package substrate and coupled to slotted waveguide antenna by the routing conductors; and mold compound covering the semiconductor die, and a portion of the multilayer package substrate.

公开(公告)号：US20230352315A1

公开(公告)日：2023-11-02

申请号：US17733921

申请日：2022-04-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Juan Alejandro Herbsommer

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/66

CPC classification number: H01L21/4857 ,  H01L23/49822 ,  H01L21/486 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L24/16

Abstract: One example includes a method for fabricating a substrate-integrated waveguide (SIW). The method includes forming a first metal layer on a carrier surface. The first metal layer can extend along an axis. The method also includes forming a first metal sidewall extending from a first edge of the first metal layer along the axis and forming a second metal sidewall extending from a second edge of the first metal layer opposite the first edge along the axis to form a trough extending along the axis. The method also includes providing a dielectric material over the first metal layer and over the first and second metal sidewalls. The method further includes forming a second metal layer over the dielectric material and over the first and second metal sidewalls. The second metal layer can extend along the axis to enclose the SIW in all radial directions along the axis.

公开(公告)号：US20230352314A1

公开(公告)日：2023-11-02

申请号：US17733998

申请日：2022-04-30

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Murugan ,  Phuong Minh Vu ,  Sylvester Ankamah-Kusi

IPC: H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L21/485 ,  H01L23/3121 ,  H01L23/49838 ,  H01L24/16 ,  H01L21/56 ,  H01L2224/16227

Abstract: Described examples include a method having steps of laying out at least two conductors and modeling conductor current through the at least two conductors to determine a current density in the at least two conductors. The method also has steps of revising the at least two conductors as adjusted conductors to add conductive material to areas of the conductor where the modeling conductor current shows above average current density; fabricating the adjusted conductors; and mounting a die to the adjusted conductors.

公开(公告)号：US11784113B2

公开(公告)日：2023-10-10

申请号：US17233110

申请日：2021-04-16

Applicant: Texas Instruments Incorporated

Inventor： Guangxu Li ,  Yiqi Tang ,  Rajen Manicon Murugan

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49811 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/1357 ,  H01L2224/13147 ,  H01L2224/16227

Abstract: A semiconductor package includes a multilayer package substrate including a top layer including a top dielectric layer and a top metal layer providing a top portion of pins on top filled vias, and a bottom layer including a bottom dielectric layer and a bottom metal layer on bottom filled vias that provide externally accessible bottom side contact pads. The top dielectric layer together with the bottom dielectric layer providing electrical isolation between the pins. And integrated circuit (IC) die that comprises a substrate having a semiconductor surface including circuitry, with nodes connected to bond pads with bonding features on the bond pads. An electrically conductive material interconnect provides a connection between the top side contact pads and the bonding features. At least a first pin includes at least one bump stress reduction structure that includes a local physical dimension change of at least 10% in at least one dimension.

公开(公告)号：US20230055211A1

公开(公告)日：2023-02-23

申请号：US17406150

申请日：2021-08-19

Applicant: Texas Instruments Incorporated

Inventor： Sylvester Ankamah-Kusi ,  Yiqi Tang ,  Rajen Manicon Murugan ,  Sreenivasan K. Koduri

IPC: H01L23/498 ,  H01L21/48

Abstract: An electronic device includes a multilevel package substrate with first and second levels extending in planes of first and second directions and spaced apart from one another along a third direction, the first level having a first side with landing areas spaced apart from one another along the first direction. The multilevel package substrate includes a conductive structure having first and second ends and conductive portions in the first and second levels that provide a conductive path along the first direction from the landing areas toward the second end, where the conductive structure includes indents that extend into the conductive portions in the first level, the indents spaced apart from one another along the first direction and positioned along the first direction between respective pairs of the landing areas.

公开(公告)号：US20220037280A1

公开(公告)日：2022-02-03

申请号：US16941818

申请日：2020-07-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Naweed Anjum ,  Liang Wan ,  Michael Gerald Amaro

IPC: H01L23/00 ,  H01L23/58 ,  H01L23/498 ,  H01L21/56

Abstract: A semiconductor package includes a first layer including a semiconductor die embedded within a dielectric substrate, and a first set of metal pillars extending through the dielectric substrate, a second layer stacked on the first layer, the second layer including a metal trace patterned on the dielectric substrate of the first layer, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer, and a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars.

公开(公告)号：US20210328367A1

公开(公告)日：2021-10-21

申请号：US17232849

申请日：2021-04-16

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Manicon Murugan

IPC: H01Q23/00 ,  H01L23/66 ,  H01Q1/22

Abstract: An AIP includes a package substrate including a top layer including a top metal layer including a first antenna type and a second antenna type, and a bottom layer including a bottom dielectric and a metal layer including a first and second contact pad and filled vias, and an IC embedded therein. Bond pads of an IC are coupled by a connection including ≥1 filled via for connecting to the top and/or bottom metal layer. A first metal pillar is between the first contact pad and first antenna, and a second metal pillar is between the second contact pad and second antenna. A first filled via is coupled to the first metal pillar providing a transmission line from the first contact pad to the first antenna. A second filled via is coupled to the first metal pillar providing a transmission line from the second contact pad to the second antenna.

公开(公告)号：US20210175326A1

公开(公告)日：2021-06-10

申请号：US17017642

申请日：2020-09-10

Applicant: Texas Instruments Incorporated

Inventor： Matthew David Romig ,  Enis Tuncer ,  Rajen Manicon Murugan ,  Yiqi Tang

IPC: H01L29/06 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: In described examples of an isolation device, an isolation die that has a set of bond pads is mounted on a first lead frame that has a set of leads. A portion of the bond pads are coupled to respective leads. A first mold material encapsulates the isolation device and the first lead frame forming a first package. The first package is mounted on a second lead frame that has a set of leads. A portion of the first lead frame leads is coupled to respective ones of the second lead frame leads. A second mold material encapsulates the first package and the second lead frame.

公开(公告)号：US10892405B2

公开(公告)日：2021-01-12

申请号：US16404978

申请日：2019-05-07

Applicant: Texas Instruments Incorporated

Inventor： Ming Li ,  Yiqi Tang ,  Jie Chen ,  Enis Tuncer ,  Usman Mahmood Chaudhry ,  Tony Ray Larson ,  Rajen Manicon Murugan ,  John Paul Tellkamp ,  Satyendra Singh Chauhan

IPC: H01L43/04 ,  H01L43/06 ,  H01L43/14 ,  G01R15/20 ,  H01L23/495 ,  G01R33/07 ,  G01R33/00

Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including ≥1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ≥1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.

公开(公告)号：US12243911B2

公开(公告)日：2025-03-04

申请号：US17017642

申请日：2020-09-10

Applicant: Texas Instruments Incorporated

Inventor： Matthew David Romig ,  Enis Tuncer ,  Rajen Manicon Murugan ,  Yiqi Tang

IPC: H01L29/06 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

Abstract: In described examples of an isolation device, an isolation die that has a set of bond pads is mounted on a first lead frame that has a set of leads. A portion of the bond pads are coupled to respective leads. A first mold material encapsulates the isolation device and the first lead frame forming a first package. The first package is mounted on a second lead frame that has a set of leads. A portion of the first lead frame leads is coupled to respective ones of the second lead frame leads. A second mold material encapsulates the first package and the second lead frame.