公开(公告)号：US20100002530A1

公开(公告)日：2010-01-07

申请号：US12557879

申请日：2009-09-11

申请人： Greg Blodgett

发明人： Greg Blodgett

IPC分类号： G11C29/00 ,  G11C17/16

CPC分类号： G11C17/16 ,  G11C29/787 ,  G11C29/812

摘要： A memory chip design methodology is disclosed wherein fuse banks on the memory chip may be implemented without enable fuses. A fuse bank may be enabled by using one or more least significant bits (LSBs) in the memory address stored in the fuse bank, thereby avoiding the need for a separate enable fuse. A reduction in the number of fuses results in space savings on the memory chip real estate and also savings in power consumption because of fewer fuses to be blown and read. With reduced fuse count, the yield of the memory chip's die may also be improved because of less number of defective fuses or failed fuse blows. The use of effective default state inversion for address fuses may further reduce the average number of fuses that need to be blown to repair a given non-redundant memory address. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

摘要翻译： 公开了一种存储器芯片设计方法，其中可以在不使能熔丝的情况下实现存储器芯片上的熔丝组。 可以通过使用存储在熔丝组中的存储器地址中的一个或多个最低有效位（LSB）来使能熔丝组，从而避免需要单独的使能熔丝。 保险丝数量的减少导致存储器芯片空间节省空间，并且由于更少的熔丝被熔化和读取而节省了功率消耗。 由于熔断器计数减少，存储器芯片的裸片的产量也可能由于缺少熔丝数量不足或保险丝熔断失败而得到改善。 对地址熔丝使用有效的默认状态反转可以进一步减少需要熔断的熔断器的平均数，以修复给定的非冗余存储器地址。 由于管理摘要的规则，本摘要不应用于解释索赔。

公开(公告)号：US07521967B2

公开(公告)日：2009-04-21

申请号：US11881262

申请日：2007-07-26

申请人： Chang Ki Kwon ,  Greg Blodgett

发明人： Chang Ki Kwon ,  Greg Blodgett

IPC分类号： H03K19/0175

CPC分类号： H03L7/00 ,  H03K19/00346

摘要： Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may each receive a data segment to transmit and a plurality of data segments that other drivers will transmit. A driver controller may adjust the time at which the data segment is transmitted in response to the plurality of data segments that the other drivers will transmit. The adjustment may compensate for simultaneous switching noise and cross-talk by, for example, delaying the transmission of a data segment or changing the slew rate of the signal carrying the data segment.

摘要翻译： 用于控制驱动器以减少数据相关噪声的技术，例如同时切换效果和串扰效应。 多个驱动器可以各自接收要发送的数据段和其他驱动器将发送的多个数据段。 驱动器控制器可以响应于其他驱动器将要发送的多个数据段来调整发送数据段的时间。 调整可以通过例如延迟数据段的传输或改变携带数据段的信号的转换速率来补偿同时的开关噪声和串扰。

公开(公告)号：US20080144398A1

公开(公告)日：2008-06-19

申请号：US11639452

申请日：2006-12-15

申请人： Greg Blodgett

发明人： Greg Blodgett

IPC分类号： H03K19/0185 ,  G11C7/10

CPC分类号： G11C7/1078 ,  G11C7/02 ,  G11C7/1084 ,  G11C11/4093 ,  H03K5/2481

摘要： An input buffer having a comparator that receives an input signal, a reference signal and a positive feedback. The comparator compares the input signal relative to the reference signal and generates an output signal transitioning between a first logic state and a second logic state responsive to the magnitude of the input signal transitioning through the magnitude of the reference signal. The comparator intensifies the output signal in response to the positive feedback from the output of the comparator while the output signal transitions from the first logic state to the second logic state.

摘要翻译： 具有接收输入信号，参考信号和正反馈的比较器的输入缓冲器。 比较器比较输入信号相对于参考信号，并且响应于输入信号的幅度在参考信号的幅度转变而产生在第一逻辑状态和第二逻辑状态之间转换的输出信号。 当输出信号从第一逻辑状态转换到第二逻辑状态时，比较器响应于来自比较器的输出的正反馈增强输出信号。

公开(公告)号：US20060203580A1

公开(公告)日：2006-09-14

申请号：US11436550

申请日：2006-05-19

申请人： Greg Blodgett

发明人： Greg Blodgett

IPC分类号： G11C29/00

CPC分类号： G11C29/02 ,  G11C17/18 ,  G11C29/027 ,  G11C29/24 ,  H03K19/1736

摘要： An antifuse latch device and method for performing a redundancy pretest without the use of additional test circuitry is disclosed. Conventional antifuse latch devices are designed such that a redundancy pretest cannot be performed on the antifuse latch device once the antifuses are programmed but rather requires additional circuitry to map the appropriate address bits to test the redundant row or column. The present invention adds a level translating inverter to a conventional antifuse latch device, thus allowing the antifuse latch device to simulate an unblown antifuse by isolating the antifuse from the latch.

公开(公告)号：US20050114803A1

公开(公告)日：2005-05-26

申请号：US10898550

申请日：2004-07-26

申请人： Aaron Schoenfeld ,  Greg Blodgett ,  Timothy Cowles

发明人： Aaron Schoenfeld ,  Greg Blodgett ,  Timothy Cowles

IPC分类号： G06F1/10 ,  G06F1/32 ,  G06F17/50 ,  H03K19/00

CPC分类号： G06F1/10 ,  G06F1/3203 ,  G06F1/3225 ,  G06F1/3275 ,  H03K19/0016 ,  Y02D10/14

摘要： A lower current input buffer is used for waking up a plurality of higher-current buffers. The lower current buffer monitors a wake-up signal and, when present, enables the higher current buffers. A higher current buffer is used to detect the sleep mode and disable the higher current buffers. A delay circuit may be used to balance the propagation delay through the circuit.

摘要翻译： 较低的电流输入缓冲器用于唤醒多个较高电流的缓冲器。 较低的当前缓冲器监视唤醒信号，并且当存在时启用较高电流缓冲器。 更高的当前缓冲区用于检测睡眠模式并禁用较高电流缓冲区。 可以使用延迟电路来平衡通过电路的传播延迟。

公开(公告)号：US07982494B2

公开(公告)日：2011-07-19

申请号：US12716822

申请日：2010-03-03

申请人： Raghu Sreeramaneni ,  Vijay Vankayala ,  Greg Blodgett

发明人： Raghu Sreeramaneni ,  Vijay Vankayala ,  Greg Blodgett

IPC分类号： H03K17/16

CPC分类号： H03K19/0005

摘要： Embodiments of the present invention include systems for calibrating an output circuit. A comparator is coupled to a calibration terminal and configured to determine whether the calibration terminal is in a first state coupled to a calibration resistor or in a second state. A calibration circuit is coupled to the calibration terminal and configured to generate a calibration value based in part on the presence or absence of the calibration resistor. An impedance selector is coupled to the calibration circuit, the comparator, and a default calibration value. The impedance selector is configured to select the default calibration value when the comparator indicates the calibration terminal is in the second state and to select the calibration value coupled from the calibration circuit when the comparator indicates the calibration terminal is in the first state.

摘要翻译： 本发明的实施例包括用于校准输出电路的系统。 比较器耦合到校准端子并且被配置为确定校准端子是处于耦合到校准电阻器的第一状态还是处于第二状态。 校准电路耦合到校准端子并且被配置为基于校准电阻器的存在或不存在而产生校准值。 阻抗选择器耦合到校准电路，比较器和默认校准值。 阻抗选择器被配置为当比较器指示校准端处于第二状态时选择默认校准值，并且当比较器指示校准端处于第一状态时选择从校准电路耦合的校准值。

公开(公告)号：US07696778B1

公开(公告)日：2010-04-13

申请号：US12355593

申请日：2009-01-16

申请人： Raghu Sreeramaneni ,  Vijay Vankayala ,  Greg Blodgett

发明人： Raghu Sreeramaneni ,  Vijay Vankayala ,  Greg Blodgett

IPC分类号： H03K17/16

CPC分类号： H03K19/0005

摘要： Embodiments of the present invention include systems for calibrating an output circuit. A comparator is coupled to a calibration terminal and configured to determine whether the calibration terminal is in a first state coupled to a calibration resistor or in a second state. A calibration circuit is coupled to the calibration terminal and configured to generate a calibration value based in part on the presence or absence of the calibration resistor. An impedance selector is coupled to the calibration circuit, the comparator, and a default calibration value. The impedance selector is configured to select the default calibration value when the comparator indicates the calibration terminal is in the second state and to select the calibration value coupled from the calibration circuit when the comparator indicates the calibration terminal is in the first state.

摘要翻译： 本发明的实施例包括用于校准输出电路的系统。 比较器耦合到校准端子并且被配置为确定校准端子是处于耦合到校准电阻器的第一状态还是处于第二状态。 校准电路耦合到校准端子并且被配置为基于校准电阻器的存在或不存在而产生校准值。 阻抗选择器耦合到校准电路，比较器和默认校准值。 阻抗选择器被配置为当比较器指示校准端处于第二状态时选择默认校准值，并且当比较器指示校准端处于第一状态时选择从校准电路耦合的校准值。

公开(公告)号：US20080036491A1

公开(公告)日：2008-02-14

申请号：US11881262

申请日：2007-07-26

申请人： Chang Kwon ,  Greg Blodgett

发明人： Chang Kwon ,  Greg Blodgett

IPC分类号： H03K19/003

CPC分类号： H03L7/00 ,  H03K19/00346

摘要： Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may each receive a data segment to transmit and a plurality of data segments that other drivers will transmit. A driver controller may adjust the time at which the data segment is transmitted in response to the plurality of data segments that the other drivers will transmit. The adjustment may compensate for simultaneous switching noise and cross-talk by, for example, delaying the transmission of a data segment or changing the slew rate of the signal carrying the data segment.

摘要翻译： 用于控制驱动器以减少数据相关噪声的技术，例如同时切换效果和串扰效应。 多个驱动器可以各自接收要发送的数据段和其他驱动器将发送的多个数据段。 驱动器控制器可以响应于其他驱动器将要发送的多个数据段来调整发送数据段的时间。 调整可以通过例如延迟数据段的传输或改变携带数据段的信号的转换速率来补偿同时的开关噪声和串扰。

公开(公告)号：US20070171752A1

公开(公告)日：2007-07-26

申请号：US11731039

申请日：2007-03-30

申请人： Donald Morgan ,  Greg Blodgett

发明人： Donald Morgan ,  Greg Blodgett

IPC分类号： G11C7/00

CPC分类号： G11C11/40622 ,  G11C5/14 ,  G11C11/406 ,  G11C11/408 ,  G11C2211/4061 ,  G11C2211/4067

摘要： A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memory cells that are refreshed at the same time to permit a relatively slow refresh rate. When transitioning from the full density mode to the half density mode, data are copied from each row of memory cells storing data to an adjacent row of memory cells. The adjacent row of memory cells are made free to store data from an adjacent row by remapping the most significant bit of the row address to the least significant bit of the row address, and then remapping all of the remaining bits of the row address to the next highest order bit.

公开(公告)号：US07212053B2

公开(公告)日：2007-05-01

申请号：US11127456

申请日：2005-05-12

申请人： Tyler Gomm ,  Greg Blodgett

发明人： Tyler Gomm ,  Greg Blodgett

IPC分类号： H03L7/06

CPC分类号： G11C7/222 ,  G11C7/1072 ,  G11C7/22 ,  H03L7/0814

摘要： A method of operating a delay locked loop is comprised of producing a first output signal in response to a first lock point. A new lock point is measured, or otherwise determined, while continuing to produce the first output signal. Thereafter, a second output signal is produced in response to the new lock point. The new lock point data may be loaded into the delay locked loop while the delay locked loop continues to produce the first output signal. The delay locked loop switches from producing the first output signal, responsive to a first lock point, to producing the second output signal, responsive to the new lock point, in response to various conditions such as control signals, e.g. an auto refresh command, a precharge all command, a mode register load command, a power down entry, a power down exit (among others), in response to a timer, e.g., an internal timer (among others), or in response to environmental condition signals, e.g., a temperature sensor output signal (among others). Circuits and systems using the disclosed method are also disclosed. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

摘要翻译： 操作延迟锁定环路的方法包括响应于第一锁定点产生第一输出信号。 在继续产生第一输出信号的同时测量或另外确定新的锁定点。 此后，响应于新的锁定点产生第二输出信号。 新的锁定点数据可以被加载到延迟锁定环路中，而延迟锁定环路继续产生第一输出信号。 响应于诸如控制信号的各种条件，响应于新的锁定点，延迟锁定环路响应于第一锁定点产生第一输出信号以产生第二输出信号。 一个自动刷新命令，一个预充电全部命令，一个模式寄存器加载命令，一个掉电输入，一个掉电退出（等等）），响应一个定时器，比如一个内部定时器（等等） 环境条件信号，例如温度传感器输出信号（等等）。 还公开了使用所公开的方法的电路和系统。 由于管理摘要的规则，本摘要不应用于解释索赔。