公开(公告)号：US20180366465A1

公开(公告)日：2018-12-20

申请号：US15996740

申请日：2018-06-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L29/04 ,  H01L29/78 ,  H01L29/161

Abstract: A semiconductor device includes PMOS and NMOS FinFET devices disposed on a hybrid substrate including a first substrate and a second substrate, in which a fin of the PMOS FinFET device is formed on the first substrate having a top surface with a (100) crystal orientation, and another fin of the NMOS FinFET device is formed on the second substrate having a top surface with a (110) crystal orientation. The semiconductor device further includes a capping layer enclosing a buried bottom portion of the fin of the PMOS FinFET device, and another capping layer enclosing an effective channel portion of the fin of the PMOS FinFET device.

公开(公告)号：US20180350969A1

公开(公告)日：2018-12-06

申请号：US15629885

申请日：2017-06-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Kuan-Ting PAN ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/16

Abstract: A semiconductor device is provided, which includes a substrate, a fin structure, a capping layer and an oxide layer. The substrate has a well. The fin structure extends from the well. The capping layer surrounds a top surface and side surfaces of the fin structure. The oxide layer is over the substrate and covers the capping layer. A thickness of a top portion of the oxide layer above the capping layer is greater than a thickness of a sidewall portion of the oxide layer.

公开(公告)号：US20170154958A1

公开(公告)日：2017-06-01

申请号：US15064402

申请日：2016-03-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ka-Hing FUNG ,  Kuo-Cheng CHING ,  Ying-Keung LEUNG

IPC: H01L29/06 ,  H01L21/306 ,  H01L29/786 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/0673 ,  H01L21/02381 ,  H01L21/30604 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78654 ,  H01L29/78684

Abstract: A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the first channel layers, a gate electrode layer disposed on the gate dielectric layer and wrapping each of the first channel layers, and a liner semiconductor layer disposed between the first channel layers and the first source/drain region.

公开(公告)号：US20170084714A1

公开(公告)日：2017-03-23

申请号：US14858862

申请日：2015-09-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Kuo-Cheng CHING ,  Ching-Wei TSAI ,  Chih-Hao WANG ,  Ying-Keung LEUNG

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/7682 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/0248 ,  H01L27/1104 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a fin structure formed over a substrate and a gate structure formed across the fin structure. The semiconductor structure further includes a bottom spacer formed on a lower part of a sidewall of the gate structure and an upper spacer formed on an upper part of the sidewall of the gate structure. In addition, the upper spacer includes an air gap formed in a dielectric material.

公开(公告)号：US20230335623A1

公开(公告)日：2023-10-19

申请号：US18298073

申请日：2023-04-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Shi-Ning JU ,  Kuan-Ting PAN ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H10B10/00

CPC classification number: H01L29/6681 ,  H01L27/0924 ,  H01L29/0653 ,  H01L21/823821 ,  H01L21/823878 ,  H10B10/12

Abstract: A first semiconductor fin is over the first region of the substrate and extends along a first direction. A second semiconductor fin is over the second region of the substrate and extends along the first direction. A dielectric structure is over the first region of the substrate and is in contact with a longitudinal end of the first semiconductor fin, wherein the dielectric structure is wider than the first semiconductor fin along a second direction perpendicular to the first direction. A first dielectric fin is over the second region of the substrate and is in contact with a longitudinal end of the second semiconductor fin, wherein the first dielectric fin and the second semiconductor fin have substantially a same width along the second direction.

公开(公告)号：US20210234036A1

公开(公告)日：2021-07-29

申请号：US17233451

申请日：2021-04-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Kuan-Ting PAN ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/16 ,  H01L21/8234

Abstract: A semiconductor device structure includes a fin structure, a semiconductive capping layer, an oxide layer, and a gate structure. The fin structure protrudes above a substrate. The semiconductive capping layer wraps around three sides of a channel region of the fin structure. The oxide layer wraps around three sides of the semiconductive capping layer. A thickness of a top portion of the semiconductive capping layer is less than a thickness of a top portion of the oxide layer. The gate structure wraps around three sides of the oxide layer.

公开(公告)号：US20200287047A1

公开(公告)日：2020-09-10

申请号：US16880864

申请日：2020-05-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shu-Hao KUO ,  Jung-Hao CHANG ,  Chao-Hsien HUANG ,  Li-Te LIN ,  Kuo-Cheng CHING

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L27/12 ,  H01L21/84 ,  H01L21/306 ,  H01L29/06 ,  H01L21/762 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/8238 ,  H01L27/092

Abstract: A device includes a semiconductor substrate, a first fin arranged over the semiconductor substrate, and an isolation structure. The first fin includes an upper portion, a bottom portion, and an insulator layer between the upper portion and the bottom portion. A top surface of the insulator layer is wider than a bottom surface of the upper portion of the first fin. The isolation structure surrounds the bottom portion of the first fin.

公开(公告)号：US20200287018A1

公开(公告)日：2020-09-10

申请号：US16881685

申请日：2020-05-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Shi-Ning JU ,  Chih-Hao WANG ,  Ying-Keung LEUNG

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092 ,  H01L21/02 ,  H01L29/51

Abstract: A semiconductor structure includes a substrate, a fin, a bottom capping structure and a top capping structure. The fin disposed on the substrate, the fin has a lower portion and an upper portion extending upwards from the lower portion. The bottom capping structure covers a sidewall of the lower portion of the fin. The top capping structure covers a sidewall of the upper portion of the fin.

公开(公告)号：US20200243666A1

公开(公告)日：2020-07-30

申请号：US16683512

申请日：2019-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHING ,  Zhi-Chang LIN ,  Kuan-Ting PAN ,  Chih-Hao WANG ,  Shi-Ning JU

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/02 ,  H01L21/768 ,  H01L29/78 ,  H01L21/033 ,  H01L21/8234

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation structure formed over a substrate, and a first stacked wire structure and a second stacked wire structure extending above the isolation structure. The semiconductor device structure includes a dummy fin structure formed over the isolation structure, and the dummy fin structure is between the first stacked wire structure and the second stacked wire structure. The semiconductor device structure also includes a capping layer formed over the dummy fin structure. The isolation structure has a first width, the dummy fin structure has a second width, and the second width is smaller than the first width.

公开(公告)号：US20200176449A1

公开(公告)日：2020-06-04

申请号：US16781485

申请日：2020-02-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHING ,  Shi Ning JU ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L27/092 ,  H01L21/28 ,  H01L21/308 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/51

Abstract: Aspects of the disclosure provide a semiconductor device and a method for forming the semiconductor device. The semiconductor device includes a plurality of nanostructures stacked over a substrate in a vertical direction, a source/drain terminal adjoining the plurality of nanostructures, and a gate structure around the plurality of nanostructures. The gate structure includes a metal cap connecting adjacent two of the plurality of nanostructures and a metal layer partially surrounding the plurality of nanostructures.