公开(公告)号：US20210082804A1

公开(公告)日：2021-03-18

申请号：US16572683

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh-Han Wu ,  Cheng-Hsiung Tsai ,  Chih Wei Lu ,  Chung-Ju Lee

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.

公开(公告)号：US20210082698A1

公开(公告)日：2021-03-18

申请号：US16571407

申请日：2019-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsi-Wen Tien ,  Wei-Hao Liao ,  Pin-Ren Dai ,  Chih Wei Lu ,  Chung-Ju Lee

IPC: H01L21/033 ,  H01L21/768

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises receiving a structure including a substrate and a first hard mask over the substrate, the first hard mask having at least two separate portions; forming spacers along sidewalls of the at least two portions of the first hard mask with a space between the spacers; forming a second hard mask in the space; forming a first cut in the at least two portions of the first hard mask; forming a second cut in the second hard mask; and depositing a cut hard mask in the first cut and the second cut.

公开(公告)号：US20210057333A1

公开(公告)日：2021-02-25

申请号：US16547732

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsiung Tsai ,  Ming-Han Lee ,  Chung-Ju Lee

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a first conductive feature in a first dielectric layer, a second conductive feature aligned with and over the first conductive feature, a first insulation layer over the first dielectric layer and the second conductive feature, a second dielectric layer over the first insulating layer, and a contact via through the first insulation layer and the second dielectric layer.

公开(公告)号：US10804143B2

公开(公告)日：2020-10-13

申请号：US16458399

申请日：2019-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-I Yang ,  Wei-Chen Chu ,  Hsin-Ping Chen ,  Chih-Wei Lu ,  Chung-Ju Lee

IPC: H01L21/768 ,  H01L23/528

Abstract: A semiconductor structure includes an integrated circuit, a first dielectric layer, an etching stop layer, a barrier layer, a conductive layer, and a second dielectric layer. The first dielectric layer is over the integrated circuit. The etching stop layer is over the first dielectric layer. The barrier layer has an upper portion extending along a top surface of the etching stop layer and a lower portion extending downwardly from the upper portion along a sidewall of the etching stop layer and a sidewall of the first dielectric layer. The conductive layer is over the barrier layer and having a void region extending through the conductive layer, the barrier layer and the etching stop layer. The second dielectric layer is over the conductive layer and the void region.

公开(公告)号：US10714421B2

公开(公告)日：2020-07-14

申请号：US15689784

申请日：2017-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Wei-Chen Chu ,  Yung-Hsu Wu ,  Chung-Ju Lee

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a conductive line over the semiconductor substrate. The semiconductor device structure also includes a conductive via on the conductive line. The conductive via has an upper portion and a protruding portion. The protruding portion extends from a bottom of the upper portion towards the conductive line. The bottom of the upper portion is wider than a top of the upper portion. The semiconductor device structure further includes a dielectric layer over the semiconductor substrate, and the dielectric layer surrounds the conductive line and the conductive via.

公开(公告)号：US10340181B2

公开(公告)日：2019-07-02

申请号：US15353850

申请日：2016-11-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-I Yang ,  Wei-Chen Chu ,  Hsin-Ping Chen ,  Chih-Wei Lu ,  Chung-Ju Lee

IPC: H01L21/768 ,  H01L23/528

Abstract: A method of forming a semiconductor structure is provided. A conductive layer is formed over a substrate. The conductive layer is selectively etched to form a first conductive portion, a second conductive portion, and a spacing between the first conductive portion and the second conductive portion. A dielectric layer is formed over the first conductive portion, the second conductive portion, and the spacing, such that an air gap is formed in the spacing between the first and second conductive portions and is sealed by the dielectric layer.

公开(公告)号：US10312136B2

公开(公告)日：2019-06-04

申请号：US15726590

申请日：2017-10-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sunil Kumar Singh ,  Chung-Ju Lee ,  Tien-I Bao

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48

Abstract: Some embodiments relate to a semiconductor device manufacturing process. In the process, a substrate is provided, and a sacrificial layer is formed over the substrate. An opening is patterned through the sacrificial layer, and the opening is filled with conductive material. The sacrificial layer is removed while the conductive material is left in place. A first dielectric layer is formed along sidewalls of the conductive material that was left in place.

公开(公告)号：US20160254225A1

公开(公告)日：2016-09-01

申请号：US15153967

申请日：2016-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lu ,  Chung-Ju Lee ,  Hsiang-Huan Lee ,  Tien-I Bao

IPC: H01L23/538 ,  H01L29/06 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/31053 ,  H01L21/32139 ,  H01L21/7682 ,  H01L21/76852 ,  H01L21/76885 ,  H01L21/76892 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/5384 ,  H01L23/5386 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure is directed to an integrated circuit. The integrated circuit has a conductive body disposed over a substrate. The conductive body has tapered sidewalls that cause an upper surface of the conductive body to have a greater width than a lower surface of the conductive body. The integrated circuit also has a projection disposed over the conductive body. The projection has tapered sidewalls that cause a lower surface of the projection to have a greater width than an upper surface of the projection and a smaller width than an upper surface of the conductive body. A dielectric material surrounds the conductive body and the projection.

Abstract translation: 本公开涉及集成电路。 集成电路具有设置在衬底上的导电体。 导电体具有锥形侧壁，其导致导电体的上表面具有比导电体的下表面更大的宽度。 集成电路还具有设置在导电体上的突起。 突起具有锥形侧壁，其使得突出部的下表面具有比突起的上表面更大的宽度，并且具有比导电体的上表面更小的宽度。 电介质材料围绕导电体和突起。

公开(公告)号：US20150243603A1

公开(公告)日：2015-08-27

申请号：US14708503

申请日：2015-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Min Huang ,  Chung-Ju Lee ,  Tien-I Bao

IPC: H01L23/532 ,  H01L23/528

CPC classification number: H01L23/5329 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02321 ,  H01L21/3105 ,  H01L21/76814 ,  H01L21/76826 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a structure and method to create a self-repairing dielectric material for semiconductor device applications. A porous dielectric material is deposited on a substrate, and exposed with treating agent particles such that the treating agent particles diffuse into the dielectric material. A dense non-porous cap is formed above the dielectric material which encapsulates the treating agent particles within the dielectric material. The dielectric material is then subjected to a process which creates damage to the dielectric material. A chemical reaction is initiated between the treating agent particles and the damage, repairing the damage. A gradient concentration resulting from the consumption of treating agent particles by the chemical reaction promotes continuous diffusion the treating agent particles towards the damaged region of the dielectric material, continuously repairing the damage.

Abstract translation: 本公开涉及一种用于为半导体器件应用创建自修复电介质材料的结构和方法。 将多孔电介质材料沉积在基底上，并用处理剂颗粒暴露，使得处理剂颗粒扩散到电介质材料中。 在电介质材料上形成致密的无孔盖，其将电介质材料中的处理剂颗粒封装起来。 然后对电介质材料进行对电介质材料造成损伤的工艺。 在处理剂颗粒和损坏之间引发化学反应，修复损坏。 通过化学反应消耗处理剂颗粒而产生的梯度浓度促使处理剂颗粒朝向电介质材料的损坏区域的连续扩散，连续地修复损伤。

公开(公告)号：US20140117561A1

公开(公告)日：2014-05-01

申请号：US14146941

申请日：2014-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sunil Kumar Singh ,  Chung-Ju Lee ,  Tien-I Bao

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76808 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1026 ,  H01L2221/1031 ,  H01L2221/1036 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a dual damascene metal interconnect for a semiconductor device. The method includes forming a layer of low-k dielectric, forming vias through the low-k dielectric layer, depositing a sacrificial layer, forming trenches through the sacrificial layer, filling the vias and trenches with metal, removing the sacrificial layer, then depositing an extremely low-k dielectric layer to fill between the trenches. The method allows the formation of an extremely low-k dielectric layer for the second level of the dual damascene structure while avoiding damage to that layer by such processes as trench etching and trench metal deposition. The method has the additional advantage of avoiding an etch stop layer between the via level dielectric and the trench level dielectric.

Abstract translation: 一种形成用于半导体器件的双镶嵌金属互连的方法。 该方法包括形成低k电介质层，通过低k电介质层形成通孔，沉积牺牲层，通过牺牲层形成沟槽，用金属填充通孔和沟槽，去除牺牲层，然后沉积 极低k电介质层填充沟槽之间。 该方法允许形成用于第二级双镶嵌结构的极低k电介质层，同时通过沟槽蚀刻和沟槽金属沉积等工艺避免对该层的损伤。 该方法具有避免通孔级电介质和沟槽级电介质之间的蚀刻停止层的额外优点。