公开(公告)号：US20210202297A1

公开(公告)日：2021-07-01

申请号：US17182782

申请日：2021-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsai-Hao HUNG ,  Ping-Cheng KO ,  Tzu-Yang LIN ,  Fang-Yu LIU ,  Cheng-Han WU

IPC: H01L21/687 ,  H01L21/677 ,  H01L21/67 ,  H05F1/00 ,  H01L21/66

Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.

公开(公告)号：US20200146154A1

公开(公告)日：2020-05-07

申请号：US16723818

申请日：2019-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Siao-Shan WANG ,  Cheng-Han WU ,  Ching-Yu CHANG ,  Chin-Hsiang LIN

IPC: H05K3/06 ,  G03F7/00 ,  G03F7/20 ,  H01L21/027 ,  G03F7/09 ,  G03F7/40

Abstract: Provided is a material composition and method that includes forming a patterned resist layer on a substrate. The patterned resist layer has a first pattern width, and the patterned resist layer has a first pattern profile having a first proportion of active sites. In some examples, the patterned resist layer is coated with a treatment material. In some embodiments, the treatment material bonds to surfaces of the patterned resist layer to provide a treated patterned resist layer having a second pattern profile with a second proportion of active sites greater than the first proportion of active sites. By way of example, and as part of the coating the patterned resist layer with the treatment material, a first pattern shrinkage process may be performed, where the treated patterned resist layer has a second pattern width less than a first pattern width.

公开(公告)号：US20190157073A1

公开(公告)日：2019-05-23

申请号：US16124063

申请日：2018-09-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hui WENG ,  Cheng-Han WU ,  Ching-Yu CHANG ,  Chin-Hsiang LIN ,  Siao-Shan WANG

IPC: H01L21/027 ,  H01L21/308 ,  G03F7/20

Abstract: Methods for forming a semiconductor structure including using a photoresist material are provided. The method for forming a semiconductor structure includes forming a material layer over a substrate and forming a photoresist layer over the material layer. The method for forming a semiconductor structure further includes performing an exposure process on the photoresist layer and developing the photoresist layer. In addition, the photoresist layer is made of a photoresist material comprising a photosensitive polymer, and the photosensitive polymer has a first photosensitive functional group bonding to a main chain of the photosensitive polymer and a first acid labile group bonding to the first photosensitive functional group.

公开(公告)号：US20180308769A1

公开(公告)日：2018-10-25

申请号：US15635308

申请日：2017-06-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuei-Ming CHANG ,  Rei-Jay HSIEH ,  Cheng-Han WU ,  Chie-Iuan LIN

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823878 ,  H01L21/76232 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate, a first source/drain feature, a second source/drain feature and a dielectric plug. The substrate has a semiconductor fin. The first source/drain feature is embedded in the semiconductor fin. The second source/drain feature is embedded in the semiconductor fin. The dielectric plug extends from above the semiconductor fin into the semiconductor fin. The dielectric plug is in between the first source/drain feature and the second source/drain feature. The dielectric plug is separated from the first source/drain feature and the second source/drain feature.