公开(公告)号：US20250147424A1

公开(公告)日：2025-05-08

申请号：US19011395

申请日：2025-01-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Hui WENG ,  Chen-Yu LIU ,  Cheng-Han WU ,  Ching-Yu CHANG ,  Chin-Hsiang LIN

IPC: G03F7/40 ,  G03F1/82 ,  G03F7/00 ,  G03F7/30 ,  G03F7/32

Abstract: A method includes illuminating radiation to a resist layer over a substrate to pattern the resist layer. The patterned resist layer is developed by using a positive tone developer. The patterned resist layer is rinsed using a basic aqueous rinse solution. A pH value of the basic aqueous rinse solution is lower than a pH value of the developer, and a rinse temperature of rinsing the patterned resist layer is in a range of about 20° C. to about 40° C.

公开(公告)号：US20230187283A1

公开(公告)日：2023-06-15

申请号：US18167442

申请日：2023-02-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuei-Ming CHANG ,  Rei-Jay HSIEH ,  Cheng-Han WU ,  Chie-Iuan LIN

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L21/823821 ,  H01L21/823814 ,  H01L21/76232 ,  H01L29/66545 ,  H01L29/7848 ,  H01L21/823481

Abstract: A device includes a first transistor, a second transistor, and a dielectric structure. The first transistor is over a substrate and has a first gate structure. The second transistor is over the substrate and has a second gate structure. The dielectric structure is between the first gate structure and the second gate structure. The dielectric structure has a width increasing from a bottom position of the dielectric structure to a first position higher than the bottom position of the dielectric structure. A width of the first gate structure is less than the width of the dielectric structure at the first position.

公开(公告)号：US20230077331A1

公开(公告)日：2023-03-16

申请号：US18055784

申请日：2022-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsai-Hao HUNG ,  Ping-Cheng KO ,  Tzu-Yang LIN ,  Fang-Yu LIU ,  Cheng-Han WU

IPC: H01L21/687 ,  H01L21/677 ,  H01L21/67 ,  H05F1/00 ,  H01L21/66

Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.

公开(公告)号：US20200159110A1

公开(公告)日：2020-05-21

申请号：US16248601

申请日：2019-01-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Hui WENG ,  Chen-Yu LIU ,  Cheng-Han WU ,  Ching-Yu CHANG ,  Chin-Hsiang LIN

IPC: G03F1/82 ,  G03F7/20

Abstract: A lithography method includes forming a resist layer over a substrate. The resist layer is exposed to radiation. The exposed resist layer is developed using a developer that removes an exposed portion of the exposed resist layer, thereby forming a patterned resist layer. The patterned resist layer is rinsed using a basic aqueous rinse solution.

公开(公告)号：US20190103306A1

公开(公告)日：2019-04-04

申请号：US16007648

申请日：2018-06-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tzu-Yang LIN ,  Cheng-Han WU ,  Ching-Yu CHANG ,  Chin-Hsiang LIN

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/033

Abstract: A method for forming openings in an underlayer includes: forming a photoresist layer on an underlayer formed on a substrate; exposing the photoresist layer; forming photoresist patterns by developing the exposed photoresist layer, the photoresist patterns covering regions of the underlayer in which the openings are to be formed; forming a liquid layer over the photoresist patterns; after forming the liquid layer, performing a baking process so as to convert the liquid layer to an organic layer in a solid form; performing an etching back process to remove a portion of the organic layer on a level above the photoresist patterns; removing the photoresist patterns, so as to expose portions of the underlayer by the remaining portion of the organic layer; forming the openings in the underlayer by using the remaining portion of the organic layer as an etching mask; and removing the remaining portion of the organic layer.

公开(公告)号：US20180164684A1

公开(公告)日：2018-06-14

申请号：US15482315

申请日：2017-04-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Ching CHANG ,  Chen-Yu LIU ,  Cheng-Han WU ,  Ching-Yu CHANG ,  Chin-Hsiang LIN

IPC: G03F7/09 ,  G03F7/039 ,  G03F7/16 ,  G03F7/20 ,  G03F7/32 ,  G03F7/38 ,  G03F7/11 ,  H01L21/027 ,  H01L21/308

CPC classification number: G03F7/38 ,  G03F7/0392 ,  G03F7/325

Abstract: A resist material and methods for forming a semiconductor structure including using the resist material are provided. The method for forming a semiconductor structure includes forming a resist layer over a substrate and exposing a portion of the resist layer to form an exposed portion of the resist layer by performing an exposure process. The method for forming a semiconductor structure further includes developing the resist layer in a developer. In addition, the resist layer is made of a resist material including a photosensitive polymer and a contrast promoter, and a protected functional group of the photosensitive polymer is deprotected to form a deprotected functional group during the exposure process, and a functional group of the contrast promoter bonds to the deprotected functional group of the photosensitive polymer.

公开(公告)号：US20210351086A1

公开(公告)日：2021-11-11

申请号：US17384888

申请日：2021-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuei-Ming CHANG ,  Rei-Jay HSIEH ,  Cheng-Han WU ,  Chie-Iuan LIN

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: An IC structure includes a semiconductor fin, first and second gate structures, and an isolation structure. The semiconductor fin extends from a substrate. The first gate structure extends above a top surface of the semiconductor fin by a first gate height. The second gate structure is over the semiconductor fin. The isolation structure is between the first and second gate structures, and has a lower dielectric portion embedded in the semiconductor fin and an upper dielectric portion extending above the top surface of the semiconductor fin by a height that is the same as the first gate height. When viewed in a cross section taken along a longitudinal direction of the semiconductor fin, the upper dielectric portion of the isolation structure has a rectangular profile with a width greater than a bottom width of the lower dielectric portion of the isolation structure.

公开(公告)号：US20210202284A1

公开(公告)日：2021-07-01

申请号：US17100218

申请日：2020-11-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tzu-Yang LIN ,  Cheng-Han WU ,  Chen-Yu LIU ,  Kuo-Shu TSENG ,  Shang-Sheng LI ,  Chen Yi HSU ,  Yu-Cheng CHANG

IPC: H01L21/67

Abstract: A lithography includes a storage tank that stores process chemical fluid, an anti-collision frame, and an integrated sensor assembly. The storage tank includes a dispensing port positioned at a lowest part of the storage tank in a gravity direction. The anti-collision frame is coupled to the storage tank. An integrated sensor assembly is disposed on at least one of the anti-collision frame and the storage tank to measure a variation in fluid quality in response to fluid quality measurement of fluid.

公开(公告)号：US20200350214A1

公开(公告)日：2020-11-05

申请号：US16933088

申请日：2020-07-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuei-Ming CHANG ,  Rei-Jay HSIEH ,  Cheng-Han WU ,  Chie-Iuan LIN

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: A device includes a semiconductor fin, a first transistor, a second transistor and a dielectric structure. The first semiconductor fin extends from a substrate. The first transistor is formed on a first region of the semiconductor fin. The second transistor is formed on a second region of the semiconductor fin laterally spaced apart from the first region of the semiconductor fin. The dielectric structure has a lower portion extending in the semiconductor fin and between the first transistor and the second transistor. The lower portion of the dielectric structure has a width increasing from a bottommost position of the dielectric structure to a first position higher than the bottommost position of the dielectric structure and decreasing from the first position to a second position higher than the first position.

公开(公告)号：US20200335386A1

公开(公告)日：2020-10-22

申请号：US16559089

申请日：2019-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsai-Hao HUNG ,  Ping-Cheng KO ,  Tzu-Yang LIN ,  Fang-Yu LIU ,  Cheng-Han WU

IPC: H01L21/687 ,  H01L21/677 ,  H01L21/67 ,  H01L21/66 ,  H05F1/00

Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.