公开(公告)号：US20200335386A1

公开(公告)日：2020-10-22

申请号：US16559089

申请日：2019-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsai-Hao HUNG ,  Ping-Cheng KO ,  Tzu-Yang LIN ,  Fang-Yu LIU ,  Cheng-Han WU

IPC: H01L21/687 ,  H01L21/677 ,  H01L21/67 ,  H01L21/66 ,  H05F1/00

Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.

公开(公告)号：US20230077331A1

公开(公告)日：2023-03-16

申请号：US18055784

申请日：2022-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsai-Hao HUNG ,  Ping-Cheng KO ,  Tzu-Yang LIN ,  Fang-Yu LIU ,  Cheng-Han WU

IPC: H01L21/687 ,  H01L21/677 ,  H01L21/67 ,  H05F1/00 ,  H01L21/66

Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.

公开(公告)号：US20210202297A1

公开(公告)日：2021-07-01

申请号：US17182782

申请日：2021-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsai-Hao HUNG ,  Ping-Cheng KO ,  Tzu-Yang LIN ,  Fang-Yu LIU ,  Cheng-Han WU

IPC: H01L21/687 ,  H01L21/677 ,  H01L21/67 ,  H05F1/00 ,  H01L21/66

Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.

公开(公告)号：US20240087945A1

公开(公告)日：2024-03-14

申请号：US18516703

申请日：2023-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsai-Hao HUNG ,  Ping-Cheng KO ,  Tzu-Yang LIN ,  Fang-Yu LIU ,  Cheng-Han WU

IPC: H01L21/687 ,  H01L21/66 ,  H01L21/67 ,  H01L21/677 ,  H05F1/00

CPC classification number: H01L21/68757 ,  H01L21/67167 ,  H01L21/67173 ,  H01L21/6719 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/67242 ,  H01L21/67742 ,  H01L22/10 ,  H05F1/00

Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.