公开(公告)号：US20210305047A1

公开(公告)日：2021-09-30

申请号：US17150356

申请日：2021-01-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Lin WEI ,  Ming-Hui WENG ,  Chih-Cheng LIU ,  Yi-Chen KUO ,  Yen-Yu CHEN ,  Yahru CHENG ,  Jr-Hung LI ,  Ching-Yu CHANG ,  Tze-Liang LEE ,  Chi-Ming YANG

IPC: H01L21/033 ,  H01L21/308 ,  G03F1/22 ,  G03F7/20

Abstract: A method of manufacturing semiconductor device includes forming a multilayer photoresist structure including a metal-containing photoresist over a substrate. The multilayer photoresist structure includes two or more metal-containing photoresist layers having different physical parameters. The metal-containing photoresist is a reaction product of a first precursor and a second precursor, and each layer of the multilayer photoresist structure is formed using different photoresist layer formation parameters. The different photoresist layer formation parameters are one or more selected from the group consisting of the first precursor, an amount of the first precursor, the second precursor, an amount of the second precursor, a length of time each photoresist layer formation operation, and heating conditions of the photoresist layers. The multilayer photoresist structure is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying developer to the selectively exposed multilayer photoresist structure to form the pattern.

公开(公告)号：US20210134589A1

公开(公告)日：2021-05-06

申请号：US17019094

申请日：2020-09-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Hui WENG ,  An-Ren ZI ,  Ching-Yu CHANG ,  Chen-Yu LIU

IPC: H01L21/027 ,  G03F7/00 ,  G03F7/11

Abstract: A method of forming a pattern in a photoresist includes forming a photoresist layer over a substrate, and selectively exposing the photoresist layer to actinic radiation to form a latent pattern. The latent pattern is developed by applying a developer composition to the selectively exposed photoresist layer to form a pattern. The developer composition includes a first solvent having Hansen solubility parameters of 15 pKa>9.5; and a second solvent having a dielectric constant greater than 18. The first solvent and the second solvent are different solvents.

公开(公告)号：US20180138050A1

公开(公告)日：2018-05-17

申请号：US15352218

申请日：2016-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yang LIN ,  Ming-Hui WENG ,  Cheng-Han WU ,  Chin-Hsiang LIN

IPC: H01L21/311 ,  H01L21/3105 ,  H01L21/027 ,  H01L29/06 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/0274 ,  H01L21/0276 ,  H01L21/31055

Abstract: Topographic planarization methods for a lithography process are provided. The method includes providing a substrate having a topography surface. A planarization stack is formed over the topography surface of the substrate. The optical material stack includes a first optical material layer and an overlying second optical material layer, and the first optical material layer has a higher etching rate than the second optical material layer with respect to an etchant. The planarization stack is etched using the etchant to entirely remove the second optical material layer and partially remove the first optical material layer, such that the remaining first optical material layer has a substantially planar surface over the topography surface of the substrate.

公开(公告)号：US20200159110A1

公开(公告)日：2020-05-21

申请号：US16248601

申请日：2019-01-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Hui WENG ,  Chen-Yu LIU ,  Cheng-Han WU ,  Ching-Yu CHANG ,  Chin-Hsiang LIN

IPC: G03F1/82 ,  G03F7/20

Abstract: A lithography method includes forming a resist layer over a substrate. The resist layer is exposed to radiation. The exposed resist layer is developed using a developer that removes an exposed portion of the exposed resist layer, thereby forming a patterned resist layer. The patterned resist layer is rinsed using a basic aqueous rinse solution.

公开(公告)号：US20200013618A1

公开(公告)日：2020-01-09

申请号：US16572286

申请日：2019-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hui WENG ,  An-Ren ZI ,  Ching-Yu CHANG ,  Chin-Hsiang LIN ,  Chen-Yu LIU

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/02

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a material layer over a substrate and forming a resist layer over the material layer. The resist layer includes an inorganic material and an auxiliary. The inorganic material includes a plurality of metallic cores and a plurality of first linkers bonded to the metallic cores. The method includes exposing a portion of the resist layer. The resist layer includes an exposed region and an unexposed region. In the exposed region, the auxiliary reacts with the first linkers. The method also includes removing the unexposed region of the resist layer by using a developer to form a patterned resist layer. The developer includes a ketone-based solvent having a formula (a) or the ester-based solvent having a formula (b).

公开(公告)号：US20250147424A1

公开(公告)日：2025-05-08

申请号：US19011395

申请日：2025-01-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Hui WENG ,  Chen-Yu LIU ,  Cheng-Han WU ,  Ching-Yu CHANG ,  Chin-Hsiang LIN

IPC: G03F7/40 ,  G03F1/82 ,  G03F7/00 ,  G03F7/30 ,  G03F7/32

Abstract: A method includes illuminating radiation to a resist layer over a substrate to pattern the resist layer. The patterned resist layer is developed by using a positive tone developer. The patterned resist layer is rinsed using a basic aqueous rinse solution. A pH value of the basic aqueous rinse solution is lower than a pH value of the developer, and a rinse temperature of rinsing the patterned resist layer is in a range of about 20° C. to about 40° C.

公开(公告)号：US20210302833A1

公开(公告)日：2021-09-30

申请号：US17071004

申请日：2020-10-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Hui WENG ,  Chen-Yu LIU ,  Chih-Cheng LIU ,  Yi-Chen KUO ,  Jia-Lin WEI ,  Yen-Yu CHEN ,  Jr-Hung LI ,  Yahru CHENG ,  Chi-Ming YANG ,  Tze-Liang LEE ,  Ching-Yu CHANG

IPC: G03F7/004 ,  G03F7/00 ,  H01L21/033

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.

公开(公告)号：US20210134746A1

公开(公告)日：2021-05-06

申请号：US17019173

申请日：2020-09-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ching-Yu CHANG ,  Ming-Da CHENG ,  Ming-Hui WENG

IPC: H01L23/00 ,  C08G73/10

Abstract: A method of manufacturing a bump structure includes forming a passivation layer over a substrate. A metal pad structure is formed over the substrate, wherein the passivation layer surrounds the metal pad structure. A polyimide layer including a polyimide is formed over the passivation layer and the metal pad structure. A metal bump is formed over the metal pad structure and the polyimide layer. The polyimide is a reaction product of a dianhydride and a diamine, wherein at least one of the dianhydride and the diamine comprises one selected from the group consisting of a cycloalkane, a fused ring, a bicycloalkane, a tricycloalkane, a bicycloalkene, a tricycloalkene, a spiroalkane, and a heterocyclic ring.

公开(公告)号：US20200319560A1

公开(公告)日：2020-10-08

申请号：US16905016

申请日：2020-06-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hui WENG ,  Ching-Yu CHANG ,  Chin-Hsiang LIN

IPC: G03F7/40 ,  H01L21/027

Abstract: Methods for performing a lithography process are provided. The method for performing a lithography process includes forming a resist layer over a substrate and exposing a portion of the resist layer to form an exposed portion between unexposed portions. The method for performing a lithography process further includes developing the resist layer to remove the exposed portion of the resist layer such that an opening is formed between the unexposed portions and forming a post treatment coating material in the opening and over the unexposed portions of the resist layer. The method for performing a lithography process further includes reacting a portion of the unexposed portions of the resist layer with the post treatment coating material by performing a post treatment process and removing the post treatment coating material.

公开(公告)号：US20190064673A1

公开(公告)日：2019-02-28

申请号：US15940107

申请日：2018-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hui WENG ,  Ching-Yu CHANG ,  Chin-Hsiang LIN

IPC: G03F7/40 ,  H01L21/027

CPC classification number: G03F7/40 ,  G03F7/20 ,  G03F7/30 ,  H01L21/0273 ,  H01L21/0274

Abstract: Methods for performing a lithography process are provided. The method for performing a lithography process includes forming a resist layer over a substrate and exposing a portion of the resist layer to form an exposed portion between unexposed portions. The method for performing a lithography process further includes developing the resist layer to remove the exposed portion of the resist layer such that an opening is formed between the unexposed portions and forming a post treatment coating material in the opening and over the unexposed portions of the resist layer. The method for performing a lithography process further includes reacting a portion of the unexposed portions of the resist layer with the post treatment coating material by performing a post treatment process and removing the post treatment coating material.