公开(公告)号：US11594606B2

公开(公告)日：2023-02-28

申请号：US17166775

申请日：2021-02-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chin Chiu ,  Chi-Ming Chen ,  Chung-Yi Yu ,  Chen-Hao Chiang

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20

Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.

公开(公告)号：US20210184011A1

公开(公告)日：2021-06-17

申请号：US17166775

申请日：2021-02-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chin Chiu ,  Chi-Ming Chen ,  Chung-Yi Yu ,  Chen-Hao Chiang

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/778

Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.

公开(公告)号：US20180308953A1

公开(公告)日：2018-10-25

申请号：US16010641

申请日：2018-06-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chin Chiu ,  Chi-Ming Chen ,  Cheng-Yuan Tsai ,  Fu-Wei Yao

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/778 ,  H01L29/205 ,  H01L23/31 ,  H01L23/29 ,  H01L29/20 ,  H01L29/10

CPC classification number: H01L29/66462 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02458 ,  H01L21/0254 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a first III/V semiconductor layer, and a second III/V semiconductor layer arranged over the first III/V semiconductor layer. Source and drain regions are arranged over the second III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

公开(公告)号：US10020376B2

公开(公告)日：2018-07-10

申请号：US15613660

申请日：2017-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chin Chiu ,  Chi-Ming Chen ,  Cheng-Yuan Tsai ,  Fu-Wei Yao

IPC: H01L29/66 ,  H01L23/29 ,  H01L29/78 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L21/02 ,  H01L23/31 ,  H01L29/10

CPC classification number: H01L29/66462 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02458 ,  H01L21/0254 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

公开(公告)号：US09818858B1

公开(公告)日：2017-11-14

申请号：US15231911

申请日：2016-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ming Chen ,  Chung-Yi Yu ,  Kuei-Ming Chen

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/04 ,  H01L21/768

CPC classification number: H01L29/7787 ,  H01L21/76871 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7786

Abstract: A transistor with a multi-layer active layer having at least one partial recess is provided. The transistor includes a channel layer arranged over a substrate. The channel layer has a first bandgap. The transistor includes a first active layer arranged over the channel layer. The first active layer has a second bandgap different from the first band gap such that the first active layer and the channel layer meet at a heterojunction. The transistor includes a second active layer arranged over the first active layer. The transistor also includes a dielectric layer arranged over the second active layer. The transistor further includes gate electrode having gate edges that are laterally adjacent to the dielectric layer. At least one gate edge of the gate edges is laterally separated from the second active layer by a first recess.

公开(公告)号：US09685525B2

公开(公告)日：2017-06-20

申请号：US15234590

申请日：2016-08-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chin Chiu ,  Chi-Ming Chen ,  Cheng-Yuan Tsai ,  Fu-Wei Yao

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/20 ,  H01L29/66 ,  H01L29/205 ,  H01L23/29 ,  H01L23/31 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/66462 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02458 ,  H01L21/0254 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

公开(公告)号：US08809910B1

公开(公告)日：2014-08-19

申请号：US13749819

申请日：2013-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ming Chen ,  Po-Chun Liu ,  Chung-Yi Yu

IPC: H01L31/072

CPC classification number: H01L29/2003 ,  H01L29/42364 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7785 ,  H01L29/7787

Abstract: The present disclosure relates to a gallium-nitride (GaN) transistor device having a composite gallium nitride layer with alternating layers of GaN and aluminum nitride (AlN). In some embodiments, the GaN transistor device has a first GaN layer disposed above a semiconductor substrate. An AlN inter-layer is disposed on the first GaN layer. A second GaN layer is disposed on the AlN inter-layer. The AlN inter-layer allows for the thickness of the GaN layer to be increased over continuous GaN layers, mitigating bowing and cracking of the GaN substrate, while improving the breakdown voltage of the disclosed GaN device.

Abstract translation: 本公开涉及具有GaN和氮化铝（AlN）交替层的复合氮化镓层的氮化镓（GaN）晶体管器件。 在一些实施例中，GaN晶体管器件具有设置在半导体衬底之上的第一GaN层。 AlN层间设置在第一GaN层上。 第二GaN层设置在AlN层间。 AlN层间层允许GaN层的厚度在连续的GaN层上增加，减轻GaN衬底的弯曲和破裂，同时改善所公开的GaN器件的击穿电压。

公开(公告)号：US20230378297A1

公开(公告)日：2023-11-23

申请号：US18366956

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ming Chen ,  Kuei-Ming Chen ,  Po-Chun Liu ,  Chung-Yi Yu

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/788

CPC classification number: H01L29/42384 ,  H01L29/785 ,  H01L29/7889

Abstract: A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.

公开(公告)号：US20230163183A1

公开(公告)日：2023-05-25

申请号：US18158192

申请日：2023-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chin Chiu ,  Chi-Ming Chen ,  Chung-Yi Yu ,  Chen-Hao Chiang

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/42364 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/2003

Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.

公开(公告)号：US11522049B2

公开(公告)日：2022-12-06

申请号：US17064811

申请日：2020-10-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuei-Ming Chen ,  Chi-Ming Chen ,  Chung-Yi Yu

IPC: H01L29/08 ,  H01L21/84 ,  H01L27/088 ,  H01L27/12 ,  H01L29/167 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/786 ,  H01L29/165 ,  H01L29/775 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device including a gate electrode over a semiconductor substrate. An epitaxial source/drain layer is disposed on the semiconductor substrate and is laterally adjacent to the gate electrode. The epitaxial source/drain layer comprises a first dopant. A diffusion barrier layer is between the epitaxial source/drain layer and the semiconductor substrate. The diffusion barrier layer comprises a barrier dopant that is different from the first dopant.