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    On-chip oscilloscope
    21.
    发明授权
    On-chip oscilloscope 有权

    公开(公告)号：US10161967B2

    公开(公告)日：2018-12-25

    申请号：US14991936

    申请日：2016-01-09

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chung-Peng Hsieh ,  Chih-Chiang Chang ,  Chung-Chieh Yang

    IPC: G01R19/00 ,  G01R13/00 ,  G01R31/28 ,  G01R13/02 ,  G01R31/317

    Abstract: A device is disclosed that includes a control circuit, a scope circuit and a time-to-current converter. The control circuit configured to delay a voltage signal for a delay time to generate a first control signal, and to generate a second control signal according to the first control signal and the voltage signal. The scope circuit configured to generate a first current signal in response to the second control signal and the voltage signal. The time-to-current converter configured to generate a second current signal according to the first control signal and the voltage signal.

    SOURCE AND DRAIN EPITAXY RE-SHAPING
    22.
    发明申请
    SOURCE AND DRAIN EPITAXY RE-SHAPING 审中-公开

    公开(公告)号：US20180366373A1

    公开(公告)日：2018-12-20

    申请号：US15625501

    申请日：2017-06-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kun-Mu LI ,  Chih-Chiang Chang ,  Wen-Chu Hsiao ,  Che-Yu Lin ,  Wei-Siang Yang

    IPC: H01L21/8234 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02 ,  H01L29/08 ,  H01L29/167 ,  H01L29/165 ,  H01L29/78

    Abstract: The present disclosure describes a method to form silicon germanium (SiGe) source/drain regions with the incorporation of a lateral etch in the epitaxial source/drain growth process. For example, the method can include forming a plurality of fins on a substrate, where each of the plurality of fins has a first width. The SiGe source/drain regions can be formed on the plurality of fins, where each SiGe source/drain region has a second width in a common direction with the first width and a height. The method can also include selectively etching—e.g., via a lateral etch—the SiGe source/drain regions to decrease the second width of the SiGe source/drain regions. By decreasing the width of the SiGe source/drain regions, electrical shorts between neighboring fins can be prevented or minimized. Further, the method can include growing an epitaxial capping layer over the Si/Ge source/drain regions.

    Source/drain formation with reduced selective loss defects
    26.
    发明授权
    Source/drain formation with reduced selective loss defects 有权

    公开(公告)号：US12154974B2

    公开(公告)日：2024-11-26

    申请号：US18521556

    申请日：2023-11-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chiang Chang ,  Ming-Hua Yu ,  Li-Li Su

    IPC: H01L29/66 ,  H01L21/20 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/417 ,  H01L29/78

    Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in an n-type Fin Field-Effect (FinFET) region and a p-type FinFET region, respectively, forming a first dielectric fin and a second dielectric fin in the n-type FinFET region and the p-type FinFET region, respectively, forming a first epitaxy mask to cover the second semiconductor fin and the second dielectric fin, performing a first epitaxy process to form an n-type epitaxy region based on the first semiconductor fin, removing the first epitaxy mask, forming a second epitaxy mask to cover the n-type epitaxy region and the first dielectric fin, performing a second epitaxy process to form a p-type epitaxy region based on the second semiconductor fin, and removing the second epitaxy mask. After the second epitaxy mask is removed, a portion of the second epitaxy mask is left on the first dielectric fin.

    Source/drain formation with reduced selective loss defects
    28.
    发明授权
    Source/drain formation with reduced selective loss defects 有权

    公开(公告)号：US11444181B2

    公开(公告)日：2022-09-13

    申请号：US17157444

    申请日：2021-01-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chiang Chang ,  Ming-Hua Yu ,  Li-Li Su

    IPC: H01L29/66 ,  H01L21/20 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/417 ,  H01L29/78

    Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in an n-type Fin Field-Effect (FinFET) region and a p-type FinFET region, respectively, forming a first dielectric fin and a second dielectric fin in the n-type FinFET region and the p-type FinFET region, respectively, forming a first epitaxy mask to cover the second semiconductor fin and the second dielectric fin, performing a first epitaxy process to form an n-type epitaxy region based on the first semiconductor fin, removing the first epitaxy mask, forming a second epitaxy mask to cover the n-type epitaxy region and the first dielectric fin, performing a second epitaxy process to form a p-type epitaxy region based on the second semiconductor fin, and removing the second epitaxy mask. After the second epitaxy mask is removed, a portion of the second epitaxy mask is left on the first dielectric fin.

    Source/Drain Formation with Reduced Selective Loss Defects
    29.
    发明申请
    Source/Drain Formation with Reduced Selective Loss Defects 有权

    公开(公告)号：US20220029001A1

    公开(公告)日：2022-01-27

    申请号：US17157444

    申请日：2021-01-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chiang Chang ,  Ming-Hua Yu ,  Li-Li Su

    IPC: H01L29/66 ,  H01L27/092 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/20

    Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in an n-type Fin Field-Effect (FinFET) region and a p-type FinFET region, respectively, forming a first dielectric fin and a second dielectric fin in the n-type FinFET region and the p-type FinFET region, respectively, forming a first epitaxy mask to cover the second semiconductor fin and the second dielectric fin, performing a first epitaxy process to form an n-type epitaxy region based on the first semiconductor fin, removing the first epitaxy mask, forming a second epitaxy mask to cover the n-type epitaxy region and the first dielectric fin, performing a second epitaxy process to form a p-type epitaxy region based on the second semiconductor fin, and removing the second epitaxy mask. After the second epitaxy mask is removed, a portion of the second epitaxy mask is left on the first dielectric fin.

    ELECTRO-MIGRATION BARRIER FOR INTERCONNECT
    30.
    发明申请
    ELECTRO-MIGRATION BARRIER FOR INTERCONNECT 有权

    公开(公告)号：US20210082831A1

    公开(公告)日：2021-03-18

    申请号：US17104534

    申请日：2020-11-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Su-Jen Sung ,  Chih-Chiang Chang ,  Chia-Ho Chen

    IPC: H01L23/532 ,  H01L21/768

    Abstract: The present disclosure relates to an integrated circuit having a conductive interconnect disposed on a dielectric over a substrate. A first liner is arranged along an upper surface of the conductive interconnect. A barrier layer is arranged along a lower surface of the conductive interconnect and contacts an upper surface of the dielectric. The barrier layer and the first liner surround the conductive interconnect. A second liner is located over the first liner and has a lower surface contacting the upper surface of the dielectric.

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