公开(公告)号：US11227889B2

公开(公告)日：2022-01-18

申请号：US16674216

申请日：2019-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsiao-Hui Tseng ,  Jhy-Jyi Sze ,  Shyh-Fann Ting ,  Tzu-Jui Wang ,  Yen-Ting Chiang ,  Yu-Jen Wang ,  Yuichiro Yamashita

IPC: H01L31/00 ,  H01L27/146

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an image sensing element disposed within a semiconductor substrate. One or more isolation structures are arranged within one or more trenches disposed along a first surface of the semiconductor substrate. The one or more isolation structures are separated from opposing sides of the image sensing element by non-zero distances. The one or more trenches are defined by sidewalls and a horizontally extending surface of the semiconductor substrate. A doped region is laterally arranged between the sidewalls of the semiconductor substrate defining the one or more trenches and is vertically arranged between the image sensing element and the first surface of the semiconductor substrate.

公开(公告)号：US20210151495A1

公开(公告)日：2021-05-20

申请号：US16684871

申请日：2019-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chiang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Jhy-Jyi Sze ,  Shyh-Fann Ting ,  Yimin Huang

IPC: H01L27/146

Abstract: The problem of reducing noise in image sensing devices, especially NIR detectors, is solved by providing ground connections for the reflectors. The reflectors may be grounded through vias that couple the reflectors to grounded areas of the substrate. The grounded areas of the substrate may be P+ doped areas formed proximate the surface of the substrate. In particular, the P+ doped areas may be parts of photodiodes. Alternatively, the reflectors may be grounded through a metal interconnect structure formed over the front side of the substrate.

公开(公告)号：US20200152675A1

公开(公告)日：2020-05-14

申请号：US16705376

申请日：2019-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sin-Yao Huang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Ming-Tsong Wang ,  Shih Pei Chou

IPC: H01L27/146

Abstract: Some embodiments relate an integrated circuit (IC). The IC includes a first substrate including an array of photodetectors, wherein a bond pad opening extends through the first substrate and is defined by an inner sidewall of the first substrate. An interconnect structure is disposed over the first substrate and includes a plurality of metal layers stacked over one another and disposed within a dielectric structure. The bond pad opening further extends through at least a portion of the interconnect structure and is further defined by an inner sidewall of the interconnect structure. A bond pad structure directly contacts a metal layer of the plurality of metal layers in the interconnect structure and is located at an uppermost extent of the bond pad opening.

公开(公告)号：US10566374B2

公开(公告)日：2020-02-18

申请号：US16167844

申请日：2018-10-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sin-Yao Huang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung

IPC: H01L27/146

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a substrate and a first interconnect wire arranged within a dielectric structure on the substrate. A bond pad contacts the first interconnect wire. A via support structure has one or more vias arranged within the dielectric structure at a location separated from the substrate by the first interconnect wire, The via support structure has a metal pattern density that is greater than or equal to approximately 19% and that is configured to mitigate damage caused by a force of a bonding process on the bond pad.

公开(公告)号：US20200013736A1

公开(公告)日：2020-01-09

申请号：US16574185

申请日：2019-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hsien Yang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Sin-Yao Huang

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/48 ,  H01L23/532 ,  H01L21/768 ,  H01L27/146

Abstract: A semiconductor device structure is provided, in some embodiments. The semiconductor device structure includes a semiconductor substrate having a first surface, a second surface, and sidewalls defining a recess that passes through the semiconductor substrate. The semiconductor device structure further includes an interconnect structure having one or more interconnect layers within a first dielectric structure that is disposed along the second surface. A conductive bonding structure is disposed within the recess and includes nickel. The conductive bonding structure has opposing outermost sidewalls that contact sidewalls of the interconnect structure.

公开(公告)号：US20190165009A1

公开(公告)日：2019-05-30

申请号：US15822701

申请日：2017-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Chuang Wu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Jen-Cheng Liu ,  Yen-Ting Chiang ,  Chun-Yuan Chen ,  Shen-Hui Hong

IPC: H01L27/146 ,  H04N5/369 ,  H04N5/374

Abstract: The present disclosure relates to a CMOS image sensor having a multiple deep trench isolation (MDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within a substrate and respectively comprising a photodiode. A boundary deep trench isolation (BDTI) structure is disposed between adjacent pixel regions, extending from a back-side of the substrate to a first depth within the substrate, and surrounding the photodiode. A multiple deep trench isolation (MDTI) structure is disposed within the individual pixel region, extending from the back-side of the substrate to a second depth within the substrate, and overlying the photodiode. A dielectric layer fills in a BDTI trench of the BDTI structure and a MDTI trench of the MDTI structure.

公开(公告)号：US20180350857A1

公开(公告)日：2018-12-06

申请号：US16043919

申请日：2018-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sin-Yao Huang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Ming-Tsong Wang ,  Shih Pei Chou

IPC: H01L27/146

Abstract: Some embodiments relate to a method. In the method, a CMOS substrate, which includes a plurality of CMOS devices, is received. An interconnect structure including a plurality of metal layers is formed over the CMOS substrate, wherein a first metal layer of the metal layers is nearest the CMOS substrate and an Nth of the metal layers is furthest from the CMOS substrate. An image sensor substrate is bonded to the interconnect structure. A first mask is formed over the image sensor substrate, and a first etch is performed with the first mask in place to expose an upper surface of the first metal layer. A conductive bond pad material is formed in direct contact with the exposed first metal layer.

公开(公告)号：US10038025B2

公开(公告)日：2018-07-31

申请号：US15380186

申请日：2016-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sin-Yao Huang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung

IPC: H01L21/44 ,  H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/14689

Abstract: Some embodiments of the present disclosure relate to an integrated chip having a via support structure underlying a bond pad. The integrated chip has an image sensing element arranged within a substrate. A bond pad region extends through the substrate, at a location laterally offset from the image sensing element, to a first metal interconnect wire arranged within a dielectric structure along a front-side of the substrate. A bond pad is arranged within the bond pad region and contacts the first metal interconnect wire. A via support structure is arranged within the dielectric structure and has one or more vias that are separated from the bond pad by the first metal interconnect wire. One or more additional vias are arranged within the dielectric structure at a location laterally offset from the bond pad region. The one or more vias have larger sizes than the one or more additional vias.

公开(公告)号：US09728570B2

公开(公告)日：2017-08-08

申请号：US14935819

申请日：2015-11-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chiang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsiao-Hui Tseng ,  Chih-Hui Huang ,  Shyh-Fann Ting ,  Shih Pei Chou ,  Sheng-Chan Li

IPC: H01L21/00 ,  H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14689

Abstract: The present disclosure relates to a BSI image sensor with improved DTI structures, and an associated method of formation. In some embodiments, the BSI image sensor comprises a plurality of image sensing elements disposed within a substrate corresponding to a plurality of pixel regions. A deep trench isolation (DTI) grid is disposed between adjacent image sensing elements and extending from an upper surface of the substrate to positions within the substrate. The DTI grid comprises air-gaps disposed under the upper surface of the substrate, the air-gaps having lower portions surrounded by a first dielectric layer and some upper portions sealed by a second dielectric layer.

公开(公告)号：US09711560B2

公开(公告)日：2017-07-18

申请号：US14562424

申请日：2014-12-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsung-Han Tsai ,  Kun-Huei Lin ,  Chun-Hao Chou ,  Tzu-Hsuan Hsu ,  Ching-Chun Wang ,  Kuo-Cheng Lee ,  Yung-Lung Hsu

IPC: H01L27/146

CPC classification number: H01L27/14649 ,  H01L27/14607 ,  H01L27/14621 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/14689

Abstract: A semiconductor device includes a substrate, light sensing devices, at least one infrared radiation sensing device, a transparent insulating layer, an infrared radiation cut layer, a color filter layer and an infrared radiation color filter layer. The light sensing devices and the at least one infrared radiation sensing device are disposed in the substrate and are adjacent to each other. The transparent insulating layer is disposed on the substrate overlying the light sensing devices and the at least one infrared radiation sensing device. The infrared radiation cut layer is disposed on the transparent insulating layer overlying the light sensing devices for filtering out infrared radiation and/or near infrared radiation. The color filter layer is disposed on the infrared radiation cut layer. The infrared radiation color filter layer is disposed on the transparent insulating layer overlying the at least one infrared radiation sensing device.