公开(公告)号：US10269770B2

公开(公告)日：2019-04-23

申请号：US15626834

申请日：2017-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sin-Yao Huang ,  Chun-Chieh Chuang ,  Ching-Chun Wang ,  Sheng-Chau Chen ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Yung-Lung Lin

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00 ,  H01L27/146 ,  H01L23/52

Abstract: In some embodiments, the present disclosure relates to a multi-dimensional integrated chip having a redistribution structure vertically extending between integrated chip die at a location laterally offset from a bond pad. The integrated chip structure has a first die and a second die. The first die has a first plurality of interconnect layers arranged within a first dielectric structure disposed on a first substrate. The second die has a second plurality of interconnect layers arranged within a second dielectric structure disposed between the first dielectric structure and a second substrate. A bond pad is disposed within a recess extending through the second substrate. A redistribution structure electrically couples the first die to the second die at a position that is laterally offset from the bond pad.

公开(公告)号：US20180026069A1

公开(公告)日：2018-01-25

申请号：US15714043

申请日：2017-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-De Wang ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Chun-Chieh Chuang ,  Jeng-Shyan Lin

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L23/481 ,  H01L27/14621 ,  H01L27/1464 ,  H01L27/14683

Abstract: An image sensor device includes a first substrate, an interconnect structure, a conductive layer, a conductive via and a second substrate. The first substrate includes a first region including a pixel array and a second region including a circuit. The interconnect structure is over the pixel array or the circuit. The interconnect structure electrically connecting the circuit to the pixel array. The conductive layer is on the interconnect structure. The conductive via passes through the second substrate and at least partially embedded in the conductive layer. The second substrate is over the conductive layer.

公开(公告)号：US20170287878A1

公开(公告)日：2017-10-05

申请号：US15626834

申请日：2017-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sin-Yao Huang ,  Chun-Chieh Chuang ,  Ching-Chun Wang ,  Sheng-Chau Chen ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Yung-Lung Lin

IPC: H01L25/065 ,  H01L25/00 ,  H01L27/146 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/49838 ,  H01L23/52 ,  H01L25/50 ,  H01L27/14634 ,  H01L27/14636 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: In some embodiments, the present disclosure relates to a multi-dimensional integrated chip having a redistribution structure vertically extending between integrated chip die at a location laterally offset from a bond pad. The integrated chip structure has a first die and a second die. The first die has a first plurality of interconnect layers arranged within a first dielectric structure disposed on a first substrate. The second die has a second plurality of interconnect layers arranged within a second dielectric structure disposed between the first dielectric structure and a second substrate. A bond pad is disposed within a recess extending through the second substrate. A redistribution structure electrically couples the first die to the second die at a position that is laterally offset from the bond pad.

公开(公告)号：US20160379960A1

公开(公告)日：2016-12-29

申请号：US14750003

申请日：2015-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sin-Yao Huang ,  Chun-Chieh Chuang ,  Ching-Chun Wang ,  Sheng-Chau Chen ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Yung-Lung Lin

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/49838 ,  H01L23/52 ,  H01L25/50 ,  H01L27/14634 ,  H01L27/14636 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: The present disclosure relates to a multi-dimensional integrated chip having a redistribution layer vertically extending between integrated chip die, which is laterally offset from a back-side bond pad. The multi-dimensional integrated chip has a first integrated chip die with a first plurality of metal interconnect layers disposed within a first inter-level dielectric layer arranged onto a front-side of a first semiconductor substrate. The multi-dimensional integrated chip also has a second integrated chip die with a second plurality of metal interconnect layers disposed within a second inter-level dielectric layer abutting the first ILD layer. A bond pad is disposed within a recess extending through the second semiconductor substrate. A redistribution layer vertically extends between the first plurality of metal interconnect layers and the second plurality of metal interconnect layers at a position that is laterally offset from the bond pad.

Abstract translation: 本发明涉及一种多维集成芯片，其具有在从背面接合焊盘侧向偏移的集成芯片裸片之间垂直延伸的再分配层。 多维集成芯片具有第一集成芯片裸片，其具有布置在第一半导体衬底的前侧上的第一级间介电层内的第一多个金属互连层。 所述多维集成芯片还具有第二集成芯片裸片，其具有设置在邻接所述第一ILD层的第二层间电介质层内的第二多个金属互连层。 接合焊盘设置在延伸穿过第二半导体衬底的凹部内。 重新分配层在从接合焊盘横向偏移的位置处在第一多个金属互连层和第二多个金属互连层之间垂直地延伸。