公开(公告)号：US20240170457A1

公开(公告)日：2024-05-23

申请号：US18425936

申请日：2024-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ying Ho ,  Jeng-Shyan Lin ,  Wen-I Hsu ,  Feng-Chi Hung ,  Dun-Nian Yaung ,  Ying-Ling Tsai

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7681 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/02 ,  H01L24/04 ,  H01L24/24 ,  H01L24/32 ,  H01L24/45 ,  H01L24/83 ,  H01L24/91 ,  H01L25/50 ,  H01L24/48 ,  H01L24/80 ,  H01L24/82 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/2405 ,  H01L2224/24146 ,  H01L2224/24147 ,  H01L2224/32146 ,  H01L2224/451 ,  H01L2224/48463 ,  H01L2224/73227 ,  H01L2224/80896 ,  H01L2224/82031 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014

Abstract: A method includes bonding a first wafer to a second wafer, with a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer bonded between a first substrate of the first wafer and a second substrate in the second wafer. A first opening is formed in the first substrate, and the first plurality of dielectric layers and the second wafer are etched through the first opening to form a second opening. A metal pad in the second plurality of dielectric layers is exposed to the second opening. A conductive plug is formed extending into the first and the second openings.

公开(公告)号：US11322540B2

公开(公告)日：2022-05-03

申请号：US17070430

申请日：2020-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chun Hsu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Jeng-Shyan Lin ,  Shyh-Fann Ting

IPC: H01L27/146 ,  H01L23/00

Abstract: The present disclosure relates to an integrated circuit. The integrated circuit includes a plurality of interconnects within a dielectric structure over a substrate. A passivation structure is arranged over the dielectric structure. The passivation structure has sidewalls connected to one or more upper surfaces of the passivation structure. A bond pad is arranged directly between the sidewalls of the passivation structure. An upper passivation layer is disposed over the passivation structure and the bond pad. The upper passivation layer extends from over an upper surface of the bond pad to within a recess in the upper surface of the bond pad.

公开(公告)号：US11222915B2

公开(公告)日：2022-01-11

申请号：US16040567

申请日：2018-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chun Hsu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Jeng-Shyan Lin ,  Shyh-Fann Ting

IPC: H01L21/00 ,  H01L27/146 ,  H01L23/00

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a plurality of interconnect layers within a dielectric structure over an upper surface of a substrate. A passivation structure is formed over the dielectric structure. The passivation structure has sidewalls and a horizontally extending surface defining has a recess within an upper surface of the passivation structure. A bond pad is formed having a lower surface overlying the horizontally extending surface and one or more protrusions extending outward from the lower surface. The one or more protrusions extend through one or more openings within the horizontally extending surface to contact a first one of the plurality of interconnect layers. An upper passivation layer is deposited on sidewalls and an upper surface of the bond pad and on sidewalls and the upper surface of the passivation structure.

公开(公告)号：US20210028219A1

公开(公告)日：2021-01-28

申请号：US17070430

申请日：2020-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chun Hsu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Jeng-Shyan Lin ,  Shyh-Fann Ting

IPC: H01L27/146 ,  H01L23/00

Abstract: The present disclosure relates to an integrated circuit. The integrated circuit includes a plurality of interconnects within a dielectric structure over a substrate. A passivation structure is arranged over the dielectric structure. The passivation structure has sidewalls connected to one or more upper surfaces of the passivation structure. A bond pad is arranged directly between the sidewalls of the passivation structure. An upper passivation layer is disposed over the passivation structure and the bond pad. The upper passivation layer extends from over an upper surface of the bond pad to within a recess in the upper surface of the bond pad.

公开(公告)号：US10153316B2

公开(公告)日：2018-12-11

申请号：US15606950

申请日：2017-05-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jeng-Shyan Lin ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Feng-Chi Hung

IPC: H01L27/146 ,  H01L31/18

Abstract: An image-sensor device is provided. The image-sensor device includes a semiconductor substrate and a radiation-sensing region in the semiconductor substrate. The image-sensor device also includes a doped isolation region adjacent to the radiation-sensing region. The image-sensor device further includes a dielectric film extending into the doped isolation region from a surface of the semiconductor substrate. A portion of the doped isolation region is between the dielectric film and the radiation-sensing region.

公开(公告)号：US09666624B2

公开(公告)日：2017-05-30

申请号：US15093285

申请日：2016-04-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jeng-Shyan Lin ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Feng-Chi Hung

IPC: H01L31/18 ,  H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14685 ,  H01L27/14689 ,  H01L31/18

Abstract: An image-sensor device is provided. The image-sensor device includes a semiconductor substrate having a front surface and a back surface, and an interconnection structure formed over the front surface. The image-sensor device also includes a radiation-sensing region in the semiconductor substrate. The image-sensor device further includes an isolation structure adjacent to the radiation-sensing region. The isolation structure includes a trench extends from the back surface, and a negatively charged film extends along an interior surface of the trench.

公开(公告)号：US11596800B2

公开(公告)日：2023-03-07

申请号：US16901884

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Ting Tsai ,  Jeng-Shyan Lin ,  Chun-Chieh Chuang ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Feng-Chi Hung

IPC: H01L25/00 ,  H01L27/06 ,  H01L27/146 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  A61N1/39

Abstract: A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component.

公开(公告)号：US20210242153A1

公开(公告)日：2021-08-05

申请号：US17236360

申请日：2021-04-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sin-Yao Huang ,  Jeng-Shyan Lin ,  Shih-Pei Chou ,  Tzu-Hsuan Hsu

IPC: H01L23/00 ,  H01L27/146

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a first isolation structure on a first surface of a substrate. A second isolation structure is formed into the first surface of the substrate. Sidewalls of the first isolation structure are disposed laterally between inner sidewalls of the second isolation structure. A bond pad is formed in the substrate such that the second isolation structure continuously laterally wraps around the bond pad.

公开(公告)号：US10790265B2

公开(公告)日：2020-09-29

申请号：US15846831

申请日：2017-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Jeng-Shyan Lin ,  Hsun-Ying Huang

IPC: H01L25/065 ,  H01L23/48 ,  H01L29/10 ,  H01L21/768 ,  H01L21/324 ,  H01L21/265

Abstract: A semiconductor device structure is provided. The semiconductor device structure has a first surface and a second surface. A first charged layer is disposed over the second surface. A dielectric layer separates a surface of the first charged layer that is closest to the semiconductor substrate from the second surface of the semiconductor substrate. A second charged layer is over the first charged layer. The first charged layer and the second charged layer are different materials and have a same charge polarity.

公开(公告)号：US10290671B2

公开(公告)日：2019-05-14

申请号：US15714043

申请日：2017-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-De Wang ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Chun-Chieh Chuang ,  Jeng-Shyan Lin

IPC: H01L27/14 ,  H01L27/146 ,  H01L23/48

Abstract: An image sensor device includes a first substrate, an interconnect structure, a conductive layer, a conductive via and a second substrate. The first substrate includes a first region including a pixel array and a second region including a circuit. The interconnect structure is over the pixel array or the circuit. The interconnect structure electrically connecting the circuit to the pixel array. The conductive layer is on the interconnect structure. The conductive via passes through the second substrate and at least partially embedded in the conductive layer. The second substrate is over the conductive layer.