公开(公告)号：US20190109125A1

公开(公告)日：2019-04-11

申请号：US16201113

申请日：2018-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ming Wu ,  Kuan-Liang Liu ,  Wen-De Wang ,  Yung-Lung Lin

IPC: H01L25/00 ,  H01L23/00 ,  H01L23/58 ,  H01L23/31 ,  H01L25/18 ,  H01L25/065

Abstract: Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3D IC includes a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The 3D IC also includes a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.

公开(公告)号：US09935147B2

公开(公告)日：2018-04-03

申请号：US15356578

申请日：2016-11-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Hung Chen ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Alexander Kalnitsky ,  Wen-De Wang

IPC: H01L27/146 ,  H01L21/762 ,  H01L21/764

CPC classification number: H01L27/1463 ,  H01L21/76232 ,  H01L21/764 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14683

Abstract: An image sensor device includes a substrate having a front surface and a back surface, and a deep trench disposed at the front surface of the substrate. The deep trench has sidewalls, a bottom and an opening. A dielectric layer is disposed along the sidewalls and the bottom of the deep trench. An epitaxial layer is disposed on the front surface of the substrate. The deep trench and the epitaxial layer collectively define an air chamber. The deep trench has a chamfered portion at an interface between the epitaxial layer and the front surface of the substrate. The chamfered portion is free of dielectric layer.

公开(公告)号：US20180026069A1

公开(公告)日：2018-01-25

申请号：US15714043

申请日：2017-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-De Wang ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Chun-Chieh Chuang ,  Jeng-Shyan Lin

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L23/481 ,  H01L27/14621 ,  H01L27/1464 ,  H01L27/14683

Abstract: An image sensor device includes a first substrate, an interconnect structure, a conductive layer, a conductive via and a second substrate. The first substrate includes a first region including a pixel array and a second region including a circuit. The interconnect structure is over the pixel array or the circuit. The interconnect structure electrically connecting the circuit to the pixel array. The conductive layer is on the interconnect structure. The conductive via passes through the second substrate and at least partially embedded in the conductive layer. The second substrate is over the conductive layer.

公开(公告)号：US11769791B2

公开(公告)日：2023-09-26

申请号：US17308381

申请日：2021-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Sheng Chu ,  Dun-Nian Yaung ,  Yu-Cheng Tsai ,  Meng-Hsien Lin ,  Ching-Chung Su ,  Jen-Cheng Liu ,  Wen-De Wang ,  Guan-Hua Chen

IPC: H01L29/66 ,  H01L29/94 ,  H01L49/02

CPC classification number: H01L28/75 ,  H01L28/87 ,  H01L28/88 ,  H01L28/92 ,  H01L29/66181 ,  H01L29/945 ,  H01L28/40

Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.

公开(公告)号：US10290671B2

公开(公告)日：2019-05-14

申请号：US15714043

申请日：2017-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-De Wang ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Chun-Chieh Chuang ,  Jeng-Shyan Lin

IPC: H01L27/14 ,  H01L27/146 ,  H01L23/48

Abstract: An image sensor device includes a first substrate, an interconnect structure, a conductive layer, a conductive via and a second substrate. The first substrate includes a first region including a pixel array and a second region including a circuit. The interconnect structure is over the pixel array or the circuit. The interconnect structure electrically connecting the circuit to the pixel array. The conductive layer is on the interconnect structure. The conductive via passes through the second substrate and at least partially embedded in the conductive layer. The second substrate is over the conductive layer.

公开(公告)号：US20220238636A1

公开(公告)日：2022-07-28

申请号：US17308381

申请日：2021-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Sheng Chu ,  Dun-Nian Yaung ,  Yu-Cheng Tsai ,  Meng-Hsien Lin ,  Ching-Chung Su ,  Jen-Cheng Liu ,  Wen-De Wang ,  Guan-Hua Chen

IPC: H01L49/02

Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.

公开(公告)号：US20230317758A1

公开(公告)日：2023-10-05

申请号：US17879556

申请日：2022-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ying Ho ,  Kuan-Hua Lin ,  Keng-Yu Chou ,  Kai-Chun Hsu ,  Sung-En Lin ,  Wen-De Wang ,  Jen-Cheng Liu

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14645 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14685

Abstract: An optical device with isolation structures and a method of fabricating the same are disclosed. The optical device includes a substrate having a first surface and a second surface opposite to the first surface, first and second radiation sensing devices disposed in the substrate, a first isolation structure disposed in the substrate. The first isolation structure has a first surface and a second surface opposite to the first surface. The optical device further includes a second isolation structure disposed in the substrate and on the first surface of the first isolation structure. The second isolation structure includes a metal structure and a dielectric layer surrounding the metal structure. The second isolation structure vertically extends over the first surface of the substrate.

公开(公告)号：US11342322B2

公开(公告)日：2022-05-24

申请号：US16933082

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ming Wu ,  Kuan-Liang Liu ,  Wen-De Wang ,  Yung-Lung Lin

IPC: H01L25/00 ,  H01L23/58 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/31

Abstract: Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3D IC includes a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The 3D IC also includes a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.

公开(公告)号：US10727218B2

公开(公告)日：2020-07-28

申请号：US16201113

申请日：2018-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ming Wu ,  Kuan-Liang Liu ,  Wen-De Wang ,  Yung-Lung Lin

IPC: H01L25/00 ,  H01L23/58 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/31

Abstract: Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3D IC includes a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The 3D IC also includes a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.

公开(公告)号：US20180175012A1

公开(公告)日：2018-06-21

申请号：US15665495

申请日：2017-08-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ming Wu ,  Kuan-Liang Liu ,  Wen-De Wang ,  Yung-Lung Lin

IPC: H01L25/00 ,  H01L23/58 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L23/3114 ,  H01L23/564 ,  H01L23/585 ,  H01L24/29 ,  H01L24/66 ,  H01L24/69 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/1161 ,  H01L2224/1162 ,  H01L2224/11845 ,  H01L2224/13147 ,  H01L2224/17517 ,  H01L2224/2745 ,  H01L2224/27462 ,  H01L2224/2761 ,  H01L2224/2762 ,  H01L2224/27845 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29015 ,  H01L2224/29019 ,  H01L2224/29035 ,  H01L2224/29147 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/83193 ,  H01L2224/83815 ,  H01L2224/83895 ,  H01L2224/8392 ,  H01L2224/83935 ,  H01L2224/83951 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A three-dimensional (3D) integrated circuit (IC) includes a first IC die and a second IC die. The first IC die includes a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The second IC die includes a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.