公开(公告)号：US11282842B2

公开(公告)日：2022-03-22

申请号：US17098269

申请日：2020-11-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Hung Lo ,  Feng-Ming Chang ,  Ying-Hsiu Kuo

IPC: H01L27/11 ,  G11C11/412 ,  G11C11/419

Abstract: A static random access memory device includes a first gate, a second gate, and a third gate. The first gate extends in a first direction from a standard threshold voltage region of a substrate to a low threshold voltage region, abutting the standard threshold voltage region, of the substrate. The second gate is disposed in the standard threshold voltage region of the substrate. The third gate is disposed in the low threshold voltage region of the substrate. The standard threshold voltage region has a boundary at an edge of the second gate. The boundary extends in a second direction different from the first direction and is crossed by the first gate. A distance between the boundary and the first gate is different from a distance between the boundary and the second gate.

公开(公告)号：US10714484B2

公开(公告)日：2020-07-14

申请号：US15953818

申请日：2018-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ming Chang ,  Chia-Hao Pao ,  Lien-Jung Hung ,  Ping-Wei Wang

IPC: H01L27/11 ,  H01L27/02 ,  H01L29/06 ,  G11C11/417 ,  G11C11/412

Abstract: An SRAM structure is provided. The SRAM structure includes a plurality of first well regions with a first doping type, a plurality of second well regions with a second doping type, a third well region with the second doping type, a plurality of first well pick-up regions, a plurality of second well pick-up regions, and a plurality of memory cells. The first well regions, the second well regions, and the third well region are formed in a semiconductor substrate. The third well region is adjacent to the second well regions. The first well pick-up regions are formed in the first well regions. The second well pick-up regions are formed in the third well region. The second well pick-up regions are shared by the third well region and the second well regions. The memory cells are formed on the first and second well regions.

公开(公告)号：US20200058564A1

公开(公告)日：2020-02-20

申请号：US16521870

申请日：2019-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Hsiu Hsu ,  Yu-Kuan Lin ,  Feng-Ming Chang ,  Hsin-Wen Su ,  Lien Jung Hung ,  Ping-Wei Wang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/762 ,  G06F17/50 ,  H01L27/11 ,  G11C11/412

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side; a first fin active region extruded from the N-well of the semiconductor substrate; a second fin active region extruded from the P-well of the semiconductor substrate; a first isolation feature formed on the N-well and the P-well and laterally contacting the first and second fin active regions, the first isolation feature having a first width; and a second isolation feature inserted between the N-well and the P-well, the second isolation feature having a second width less than the first width.

公开(公告)号：US09620509B1

公开(公告)日：2017-04-11

申请号：US14928685

申请日：2015-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hao Pao ,  Chang-Ta Yang ,  Feng-Ming Chang ,  Ping-Wei Wang

IPC: H01L27/11 ,  H01L27/02

CPC classification number: H01L27/1104 ,  G11C5/06 ,  G11C5/063 ,  G11C11/412 ,  G11C11/4125 ,  G11C11/419 ,  H01L23/528 ,  H01L27/1116 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/7827

Abstract: An SRAM includes an SRAM array including a plurality of SRAM cells arranged in a matrix. Each of the SRAM cells includes six vertical field effect transistors. The SRAM array includes a plurality of groups of conductive regions extending in the column direction. Each of the plurality of groups of conductive regions includes a first to a fourth conductive region arranged in this order in the row direction, and the first to fourth conductive regions are separated by insulating regions from each other. The first, second and third conductive regions are coupled to sources of first conductive type VFETs, and the fourth conductive region is coupled to sources of second conductive type VFETs. The plurality of groups are arranged in the row direction such that the fourth conductive region of one group of conductive regions is adjacent to the first conductive region of adjacent one group of conductive regions.

公开(公告)号：US20240196585A1

公开(公告)日：2024-06-13

申请号：US18581604

申请日：2024-02-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ming Chang ,  Kuo-Hsiu Hsu

IPC: H10B10/00 ,  H01L21/768 ,  H01L23/485 ,  H01L27/02 ,  H10B99/00

CPC classification number: H10B10/12 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/0207 ,  H10B99/00 ,  H01L2924/0002

Abstract: Systems and methods are provided for forming an intra-connection structure. A first gate structure and a first source/drain region adjacent to the first gate structure is formed on a substrate. A first dielectric material is disposed on the first source/drain region. A spacer material is formed on the first gate structure. The first dielectric material is removed to expose at least part of the first source/drain region. At least part of the spacer material is removed to expose at least part of the first gate structure. A first conductive material is formed between the first gate structure and the first source/drain region to electrically connect the first source/drain region and the first gate structure.

公开(公告)号：US11937415B2

公开(公告)日：2024-03-19

申请号：US17874463

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Kuo-Hsiu Hsu ,  Feng-Ming Chang ,  Wen-Chun Keng ,  Lien Jung Hung

IPC: H10B10/00

CPC classification number: H10B10/12 ,  H10B10/18

Abstract: A method of forming a semiconductor device includes providing a substrate including a circuit region and a well strap region, forming a mandrel extending from the circuit region to the well strap region, depositing mandrel spacers on sidewalls of the mandrel, removing the mandrel in the circuit region, while the mandrel in the well strap region remains intact, patterning the substrate with the mandrel spacers in the circuit region and the mandrel in the well strap region as an etch mask, thereby forming at least a first fin in the circuit region and a second fin in the well strap region, and epitaxially growing a first epitaxial feature over the first fin in the circuit region and a second epitaxial feature over the second fin in the well strap region. A width of the second fin is larger than a width of the first fin.

公开(公告)号：US20230328948A1

公开(公告)日：2023-10-12

申请号：US18333197

申请日：2023-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Hsiu Hsu ,  Yu-Kuan Lin ,  Feng-Ming Chang ,  Lien-Jung Hung ,  Ping-Wei Wang

IPC: H10B10/00 ,  H01L27/092 ,  G11C11/419 ,  G11C11/412 ,  G11C11/413

CPC classification number: H10B10/12 ,  H01L27/0924 ,  G11C11/413 ,  G11C11/412 ,  G11C11/419

Abstract: A semiconductor device includes first, second, third, fourth, and fifth active regions each extending lengthwise along a first direction, and first, second, third, fourth, fifth, and sixth gates each extending lengthwise along a second direction perpendicular to the first direction. The first, second, third, and fourth active regions comprise channel regions and source/drain (S/D) regions of first, second, third, and fourth transistors respectively, and the fifth active region comprises channel regions and S/D regions of fifth and sixth transistors. The first through sixth gates are configured to engage the channel regions of the first through sixth transistors respectively. The first, second, and fifth gates are electrically connected. The fifth active region is disposed between the second and third active regions.

公开(公告)号：US11527539B2

公开(公告)日：2022-12-13

申请号：US16888269

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Hsiu Hsu ,  Feng-Ming Chang ,  Kian-Long Lim ,  Ping-Wei Wang ,  Lien Jung Hung ,  Ruey-Wen Chang

IPC: G11C7/12 ,  H01L27/11 ,  G11C8/08 ,  G11C11/412 ,  G11C11/417

Abstract: A semiconductor structure includes an SRAM cell that includes first and second pull-up (PU) transistors, first and second pull-down (PD) transistors, first and second pass-gate (PG) transistors, and bit line (BL) conductors. The first PU and the first PD transistors form a first inverter. The second PU and the second PD transistors form a second inverter. The first and the second inverters are cross-coupled to form two storage nodes that are coupled to the BL conductors through the first and the second PG transistors. The first and the second PU transistors are formed over an n-type active region over a frontside of the semiconductor structure. The first and the second PD transistors and the first and the second PG transistors are formed over a p-type active region over the frontside of the semiconductor structure. The BL conductors are disposed over a backside of the semiconductor structure.

公开(公告)号：US20220352365A1

公开(公告)日：2022-11-03

申请号：US17812874

申请日：2022-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Kuo-Hsiu Hsu ,  Feng-Ming Chang ,  Kian-Long Lim ,  Lien Jung Hung

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L27/088 ,  H01L29/66 ,  H01L29/16

Abstract: A semiconductor device including nanosheet field-effect transistors (NSFETs) in a first region and fin field-effect transistors (FinFETs) in a second region and methods of forming the same are disclosed. In an embodiment, a device includes a first memory cell, the first memory cell including a first transistor including a first channel region, the first channel region including a first plurality of semiconductor nanostructures; and a second transistor including a second channel region, the second channel region including a semiconductor fin.

公开(公告)号：US11201158B2

公开(公告)日：2021-12-14

申请号：US16921173

申请日：2020-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ming Chang ,  Chia-Hao Pao ,  Lien-Jung Hung ,  Ping-Wei Wang

IPC: H01L27/11 ,  H01L27/02 ,  H01L29/06 ,  G11C11/417 ,  G11C11/412

Abstract: An SRAM structure is provided. The SRAM structure includes a plurality of first well regions with a first doping type, a second well region with a second doping type, a plurality of first well pick-up regions, a plurality of second well pick-up regions and a plurality of memory cells. The first well regions are formed in a semiconductor substrate. The second well region is formed in the semiconductor substrate. The first well pick-up regions are formed in the first well regions. The second well pick-up regions are formed in the second well region. Each of the memory cells is disposed on two adjacent first well regions and a portion of the second well region between the two adjacent first well regions. Each of the first well pick-up regions is disposed between two adjacent second well pick-up regions.