公开(公告)号：US20180166476A1

公开(公告)日：2018-06-14

申请号：US15452935

申请日：2017-03-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kai-Yi Chen ,  Chih-Fei Lee ,  Fu-Cheng Chang ,  Ching-Hung Kao ,  Chia-Pin Cheng

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14621 ,  H01L27/14685 ,  H01L27/14687

Abstract: A semiconductor device and a method for fabricating the same are provided. In the method for fabricating the semiconductor device, at first, a semiconductor substrate is provided. Then, a trench is formed in the semiconductor substrate. Thereafter, a dielectric layer is formed to cover the semiconductor substrate, in which the dielectric layer has a trench portion located in the trench of the semiconductor substrate. Then, a reflective material layer is formed on the trench portion of the dielectric layer. Thereafter, the reflective material layer is etched to form an isolation structure, in which the isolation structure includes a top portion located on the semiconductor substrate and a bottom portion located in a trench formed by the trench portion of the dielectric layer.

公开(公告)号：US09997628B1

公开(公告)日：2018-06-12

申请号：US15486616

申请日：2017-04-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Hsiang Tseng ,  Jheng-Hong Jiang ,  Fu-Cheng Chang ,  Ching-Hung Kao ,  Hsin-Chi Chen

IPC: H01L29/78 ,  H01L21/82 ,  H01L29/49 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L29/7833 ,  H01L21/823814 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/1033 ,  H01L29/4916 ,  H01L29/66492

Abstract: The present disclosure provides a semiconductor device and a method of fabricating the semiconductor device. In some embodiments, the semiconductor device includes a substrate having a well region, a first source/drain region, a second source/drain region, a buried channel and a gate structure. The first source/drain region is located within the well region. The gate structure includes a co-doped gate including polysilicon and having a first concentration of a n-type impurity and a second concentration of a p-type impurity, in which the n-type impurity and the p-type impurity are mixed and distributed.

公开(公告)号：US20180138218A1

公开(公告)日：2018-05-17

申请号：US15353835

申请日：2016-11-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Pin Cheng ,  Fu-Cheng Chang ,  Ching-Hung Kao ,  Che-Chun Lu

IPC: H01L27/146

CPC classification number: H01L27/14603 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14689

Abstract: An image sensor and a fabrication method thereof are provided. In the fabrication method of the image sensor, at first, two isolation features are formed in a substrate to define a pixel region. Then, a floating node and a pinning layer are formed in one of the isolation features, in which a space region is located between the floating node and the pinning layer, and the floating node has a first conductivity type different from a second conductivity type of the pinning layer. Thereafter, a light-sensitive element is formed in the pixel region, and a transfer gate is formed on the pixel region, thereby forming a pixel. Since there is a space region located between the floating node and the pinning layer, a leakage path between the floating node and the pinning layer can be prevented.

公开(公告)号：US20170345852A1

公开(公告)日：2017-11-30

申请号：US15228071

申请日：2016-08-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Hung Lee ,  Chia-Pin Cheng ,  Fu-Cheng Chang ,  Volume Chien ,  Ching-Hung Kao

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14609 ,  H01L27/14614 ,  H01L27/1462 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14689

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate. An isolation feature is disposed in the semiconductor substrate to define a pixel region and a periphery region of the semiconductor substrate. A transistor gate is formed on the semiconductor substrate in the pixel region, in which the transistor gate has a first sidewall and a second sidewall opposite to the first sidewall. A photodiode is disposed in the semiconductor substrate and adjacent to the second sidewall of the transistor gate. A patterned spacer layer is formed on the photodiode and on the transistor gate. The patterned spacer layer includes a first sidewall spacer on the first sidewall of the transistor gate, and a protective structure covering the photodiode and a top surface of the transistor gate.

公开(公告)号：US09431446B2

公开(公告)日：2016-08-30

申请号：US14135042

申请日：2013-12-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Volume Chien ,  Fu-Cheng Chang ,  Yi-Hsing Chu ,  Shiu-Ko Jangjian ,  Chi-Cherng Jeng

IPC: H01L27/14 ,  H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/1464

Abstract: Embodiments of mechanisms for forming an image sensor device are provided. The image sensor device includes a semiconductor substrate and an isolation structure in the semiconductor substrate. The image sensor device also includes an active region in the semiconductor substrate and surrounded by the isolation structure. The active region includes a light sensing region and a doped region, and the doped region has a horizontal length and a vertical length. A ratio of the horizontal length to the vertical length is in a range from about 1 to about 4.

Abstract translation: 提供了用于形成图像传感器装置的机构的实施例。 图像传感器装置包括半导体衬底和半导体衬底中的隔离结构。 图像传感器装置还包括半导体衬底中的有源区并被隔离结构包围。 有源区包括光感测区和掺杂区，掺杂区具有水平长度和垂直长度。 水平长度与垂直长度的比率在约1至约4的范围内。

公开(公告)号：US20240021469A1

公开(公告)日：2024-01-18

申请号：US18356843

申请日：2023-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ssu-Chiang Weng ,  Ping-Hao Lin ,  Fu-Cheng Chang

IPC: H01L21/768 ,  H01L25/065 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L23/48 ,  H01L21/311

CPC classification number: H01L21/76832 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/76805 ,  H01L25/0657 ,  H01L21/76807 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/481 ,  H01L21/31116

Abstract: A method includes bonding a first wafer to a second wafer. The first wafer includes a plurality of dielectric layers, a metal pipe penetrating through the plurality of dielectric layers, and a dielectric region encircled by the metal pipe. The dielectric region has a plurality of steps formed of sidewalls and top surfaces of portions of the plurality of dielectric layers that are encircled by the metal pipe. The method further includes etching the first wafer to remove the dielectric region and to leave an opening encircled by the metal pipe, extending the opening into the second wafer to reveal a metal pad in the second wafer, and filling the opening with a conductive material to form a conductive plug in the opening.

公开(公告)号：US11791205B2

公开(公告)日：2023-10-17

申请号：US17238496

申请日：2021-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ssu-Chiang Weng ,  Ping-Hao Lin ,  Fu-Cheng Chang

IPC: H01L25/065 ,  H01L23/522 ,  H01L21/768 ,  H01L23/31 ,  H01L23/528 ,  H01L23/48 ,  H01L21/311

CPC classification number: H01L21/76832 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0657

Abstract: A method includes bonding a first wafer to a second wafer. The first wafer includes a plurality of dielectric layers, a metal pipe penetrating through the plurality of dielectric layers, and a dielectric region encircled by the metal pipe. The dielectric region has a plurality of steps formed of sidewalls and top surfaces of portions of the plurality of dielectric layers that are encircled by the metal pipe. The method further includes etching the first wafer to remove the dielectric region and to leave an opening encircled by the metal pipe, extending the opening into the second wafer to reveal a metal pad in the second wafer, and filling the opening with a conductive material to form a conductive plug in the opening.

公开(公告)号：US11515435B2

公开(公告)日：2022-11-29

申请号：US17067548

申请日：2020-10-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Hsiang Tseng ,  Chih-Fei Lee ,  Chia-Pin Cheng ,  Fu-Cheng Chang

IPC: H01L31/0216 ,  H01L31/0232 ,  H01L27/146 ,  H01L31/112

Abstract: A semiconductor device includes a semiconductor substrate, a photo sensing region, and a plurality of nanostructures. The semiconductor substrate has a first dopant. The photo sensing region is embedded in the semiconductor substrate, has a top surface level with a top surface of the semiconductor substrate, and has a second dopant that is of a different conductivity type than the first dopant. The plurality of nanostructures is on the photo sensing region and is made of a material the same as the photo sensing region.

公开(公告)号：US10804211B2

公开(公告)日：2020-10-13

申请号：US16022896

申请日：2018-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

Inventor： Kuo-Hung Lee ,  Chih-Fei Lee ,  Fu-Cheng Chang ,  Ching-Hung Kao

IPC: H01L23/544 ,  H01L21/78 ,  H01L23/522 ,  H01L23/528 ,  H01L49/02

Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.

公开(公告)号：US10157941B2

公开(公告)日：2018-12-18

申请号：US15353835

申请日：2016-11-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Pin Cheng ,  Fu-Cheng Chang ,  Ching-Hung Kao ,  Che-Chun Lu

IPC: H01L31/062 ,  H01L27/146

Abstract: An image sensor and a fabrication method thereof are provided. In the fabrication method of the image sensor, at first, two isolation features are formed in a substrate to define a pixel region. Then, a floating node and a pinning layer are formed in one of the isolation features, in which a space region is located between the floating node and the pinning layer, and the floating node has a first conductivity type different from a second conductivity type of the pinning layer. Thereafter, a light-sensitive element is formed in the pixel region, and a transfer gate is formed on the pixel region, thereby forming a pixel. Since there is a space region located between the floating node and the pinning layer, a leakage path between the floating node and the pinning layer can be prevented.