公开(公告)号：US10593775B2

公开(公告)日：2020-03-17

申请号：US16228872

申请日：2018-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yee-Chia Yeo ,  Sung-Li Wang ,  Chi On Chui ,  Jyh-Cherng Sheu ,  Hung-Li Chiang ,  I-Sheng Chen

IPC: H01L29/45 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L23/522 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.

公开(公告)号：US10283414B2

公开(公告)日：2019-05-07

申请号：US15628345

申请日：2017-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Sheng Chen ,  Tzu-Chiang Chen ,  Chih-Sheng Chang ,  Cheng-Hsien Wu

IPC: H01L21/8234 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06

Abstract: A method of forming a semiconductor device includes providing a semiconductor structure that includes a first semiconductor material extending from a first region to a second region. The method further includes removing a portion of the first semiconductor material in the second region to form a recess, where the recess exposes a sidewall of the first semiconductor material disposed in the first region; forming a dielectric material covering the sidewall; while the dielectric material covers the sidewall, epitaxially growing a second semiconductor material in the second region adjacent the dielectric material; and forming a first fin including the first semiconductor material and a second fin including the second semiconductor material.

公开(公告)号：US10269934B2

公开(公告)日：2019-04-23

申请号：US15590243

申请日：2017-05-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Sheng Chen ,  Cheng-Hsien Wu ,  Chih-Chieh Yeh

IPC: H01L29/66 ,  H01L29/10 ,  H01L27/088 ,  H01L21/285

Abstract: A semiconductor device includes a substrate, at least one first semiconductor layer, and at least one second semiconductor layer. The at least one first semiconductor layer is disposed on the substrate, and the at least one second semiconductor layer is disposed on the at least one first semiconductor layer. The at least one first semiconductor layer includes a first doping portion, a second doping portion, a channel, and a semiconductor film. The second doping portion is adjacent to the first doping portion. The channel is disposed between the first doping portion and the second doping portion, and disposed with the substrate in parallel. The semiconductor film is disposed around the channel.

公开(公告)号：US10163628B1

公开(公告)日：2018-12-25

申请号：US15704992

申请日：2017-09-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Wu ,  I-Sheng Chen

IPC: H01L31/072 ,  H01L31/109 ,  H01L21/02 ,  H01L29/04 ,  H01L29/06 ,  H01L29/78 ,  H01L29/165 ,  H01L29/20 ,  H01L29/66 ,  H01L29/267

Abstract: A structure includes a substrate including a first semiconductor material; a dielectric feature embedded in the substrate; and a second semiconductor material embedded in the substrate, the second semiconductor material having lattice mismatch to the first semiconductor material, the second semiconductor material having two upper sidewalls and two lower sidewalls, the two upper sidewalls in contact with the dielectric feature, the two lower sidewalls in contact with the substrate, the two lower sidewalls being non-perpendicular to a top surface of the substrate, a bottommost portion of the dielectric feature being lower than a topmost portion of the two lower sidewalls.

公开(公告)号：US10134640B1

公开(公告)日：2018-11-20

申请号：US15652628

申请日：2017-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  I-Sheng Chen ,  Tzu-Chiang Chen ,  Chao-Ching Cheng ,  Chih-Chieh Yeh ,  Yee-Chia Yeo

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786 ,  H01L27/092 ,  H01L21/02

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes a gate structure over the fin portion and extending across the fin portion. The semiconductor device structure includes a first semiconductor wire over the fin portion and passing through the gate structure. The semiconductor device structure includes a second semiconductor wire over the first semiconductor wire and passing through the gate structure. The gate structure surrounds the second semiconductor wire and separates the first semiconductor wire from the second semiconductor wire. The first semiconductor wire and the second semiconductor wire are made of different materials.

公开(公告)号：US10121870B1

公开(公告)日：2018-11-06

申请号：US15692169

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  I-Sheng Chen ,  Tzu-Chiang Chen

IPC: H01L21/70 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes semiconductor wires stacked over the fin structure. The semiconductor device structure further includes a gate stack over the fin structure. The semiconductor wires are surrounded by the gate stack. In addition, the semiconductor device structure includes source or drain structures over the fin structure and on opposite sides of the semiconductor wires. The semiconductor device structure also includes strain-relaxed buffer structures between the source or drain structures and the fin structure. The strain-relaxed buffer structures and the semiconductor wires have different lattice constants.

公开(公告)号：US09627540B1

公开(公告)日：2017-04-18

申请号：US15157139

申请日：2016-05-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Sheng Chen ,  Chih Chieh Yeh ,  Cheng-Hsien Wu

IPC: H01L29/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/161 ,  H01L29/16

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on each of the first channel layers, a gate electrode layer disposed on the gate dielectric. Each of the first channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire passes through the first source/drain region and enters into an anchor region. At the anchor region, the semiconductor wire has no gate electrode layer and no gate dielectric, and is sandwiched by a second semiconductor material.

公开(公告)号：US09583399B1

公开(公告)日：2017-02-28

申请号：US15098073

申请日：2016-04-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Sheng Chen ,  Cheng-Hsien Wu ,  Chih Chieh Yeh

IPC: H01L21/306 ,  H01L21/8238 ,  H01L29/24 ,  H01L29/16 ,  H01L29/423 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L29/78618 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7853 ,  H01L29/78696

Abstract: A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the first channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the first channel layers. Each of the first channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire extends into the first source/drain region. The semiconductor wire in the first source/drain regions is wrapped around by a second semiconductor material.

Abstract translation: 半导体器件包括设置在衬底上的第一沟道层，设置在衬底上的第一源/漏区，设置在每个第一沟道层上并包围第一沟道层的栅极电介质层，以及设置在栅极电介质层上的栅电极层和 缠绕每个第一通道层。 每个第一沟道层包括由第一半导体材料制成的半导体线。 半导体线延伸到第一源/漏区。 第一源极/漏极区域中的半导体线被第二半导体材料缠绕。

公开(公告)号：US12237229B2

公开(公告)日：2025-02-25

申请号：US18323764

申请日：2023-05-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Sheng Chen ,  Yi-Jing Li ,  Chen-Heng Li

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/321 ,  H01L21/762 ,  H01L27/088 ,  H01L29/66

Abstract: The present disclosure describes a method that includes forming a fin protruding from a substrate, the fin including a first sidewall and a second sidewall formed opposite to the first sidewall. The method also includes depositing a shallow-trench isolation (STI) material on the substrate. Depositing the STI material includes depositing a first portion of the STI material in contact with the first sidewall and depositing a second portion of the STI material in contact with the second sidewall. The method also includes performing a first etching process on the STI material to etch the first portion of the STI material at a first etching rate and the second portion of the STI material at a second etching rate greater than the first etching rate. The method also includes performing a second etching process on the STI material to etch the first portion of the STI material at a third etching rate and the second portion of the STI material at a fourth etching rate less than the third etching rate.

公开(公告)号：US11195926B2

公开(公告)日：2021-12-07

申请号：US16681102

申请日：2019-11-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching Cheng ,  Yu-Lin Yang ,  I-Sheng Chen ,  Tzu-Chiang Chen

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/786

Abstract: A gate-all-around structure including a first transistor is provided. The first transistor includes a semiconductor substrate having a top surface, and a first nanostructure over the top surface of the semiconductor substrate and between a first source and a first drain. The first transistor also includes a first gate structure around the first nanostructure, and an inner spacer between the first gate structure and the first source, wherein an interface between the inner spacer and the first gate structure is non-flat. The first transistor includes an isolation layer between the top surface of the semiconductor substrate and the first source and the first drain.