公开(公告)号：US20160071799A1

公开(公告)日：2016-03-10

申请号：US14477689

申请日：2014-09-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Jia HSIEH ,  Long-Jie HONG ,  Chih-Lin WANG ,  Kang-Min KUO

IPC: H01L23/535 ,  H01L29/161 ,  H01L29/45 ,  H01L21/02 ,  H01L29/78 ,  H01L21/768 ,  H01L21/285 ,  H01L21/321 ,  H01L29/66 ,  H01L29/16 ,  H01L21/311

CPC classification number: H01L21/76831 ,  H01L21/02063 ,  H01L21/28518 ,  H01L21/31105 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76855 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66568 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device includes a substrate, an epi-layer, a first etch stop layer, an interlayer dielectric (ILD) layer, a second etch stop layer, a protective layer, a liner, a silicide cap and a contact plug. The substrate has a first portion and a second portion. The epi-layer is disposed in the first portion. The first etch stop layer is disposed on the second portion. The ILD layer is disposed on the first etch stop layer. The second etch stop layer is disposed on the ILD layer, in which the first etch stop layer, the ILD layer and the second etch stop layer form a sidewall surrounding the first portion. The protective layer is disposed on the sidewall. The liner is disposed on the protective layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the liner.

Abstract translation: 半导体器件包括衬底，外延层，第一蚀刻停止层，层间电介质（ILD）层，第二蚀刻停止层，保护层，衬垫，硅化物帽和接触插塞。 基板具有第一部分和第二部分。 外延层设置在第一部分中。 第一蚀刻停止层设置在第二部分上。 ILD层设置在第一蚀刻停止层上。 第二蚀刻停止层设置在ILD层上，其中第一蚀刻停止层，ILD层和第二蚀刻停止层形成围绕第一部分的侧壁。 保护层设置在侧壁上。 衬垫设置在保护层上。 硅化物盖设置在外延层上。 接触插头设置在硅化物盖上并被衬垫包围。

公开(公告)号：US20210335662A1

公开(公告)日：2021-10-28

申请号：US17365911

申请日：2021-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Jia HSIEH ,  Long-Jie HONG ,  Chih-Lin WANG ,  Kang-Min KUO

IPC: H01L21/768 ,  H01L29/16 ,  H01L29/161 ,  H01L29/45 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L23/485 ,  H01L21/8238 ,  H01L29/165

Abstract: A device includes an isolation structure, a source/drain epi-layer, a contact, a first dielectric layer, and a second dielectric layer. The isolation structure is embedded in a substrate. The source/drain epi-layer is embedded in the substrate and is in contact with the isolation structure. The contact is over the source/drain epi-layer. The first dielectric layer wraps the contact. The second dielectric layer is between the contact and the first dielectric layer. The first and second dielectric layers include different materials, and a portion of the source/drain epi-layer is directly between a bottom portion of the second dielectric layer and a top portion of the isolation structure.

公开(公告)号：US20200312719A1

公开(公告)日：2020-10-01

申请号：US16901815

申请日：2020-06-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Long-Jie HONG ,  Chih-Lin WANG ,  Kang-Min KUO

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device includes an active area having source and drain regions and a channel region between the source and drain regions, an isolation structure surrounding the active area, and a gate structure over the channel region of the active area and over the isolation structure, wherein the isolation structure has a first portion under the gate structure and a second portion free from coverage by the gate structure, and a top of the first portion of the isolation structure is lower than a top of the second portion of the isolation structure.

公开(公告)号：US20200044016A1

公开(公告)日：2020-02-06

申请号：US16595100

申请日：2019-10-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei LIN ,  Chih-Lin WANG ,  Kang-Min KUO

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

公开(公告)号：US20200006336A1

公开(公告)日：2020-01-02

申请号：US16443416

申请日：2019-06-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen LUNG ,  Long-Jie HONG ,  Kang-Min KUO

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/285 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/24 ,  H01L29/16 ,  H01L29/08

Abstract: A method of manufacturing a semiconductor device includes forming a first transistor structure and a second transistor structure on a substrate, wherein source/drain structures of the first transistor structure and the second transistor structure are merged. The first and second transistor structures are separated by etching the source/drain structures.

公开(公告)号：US20180337174A1

公开(公告)日：2018-11-22

申请号：US16048744

申请日：2018-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cong-Min FANG ,  Chih-Lin WANG ,  Kang-Min KUO

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/8234 ,  H01L27/02

CPC classification number: H01L27/088 ,  H01L21/32139 ,  H01L21/823456 ,  H01L27/0207 ,  H01L29/4916 ,  H01L29/66545

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first source region, a second source region, a first drain region, and a second drain region. The semiconductor device structure includes a first gate structure over the substrate and between the first source region and the first drain region. The semiconductor device structure includes a second gate structure over the substrate and between the second source region and the second drain region. A first thickness of the first gate structure is greater than a second thickness of the second gate structure. A first gate width of the first gate structure is less than a second gate width of the second gate structure.

公开(公告)号：US20170170170A1

公开(公告)日：2017-06-15

申请号：US14970036

申请日：2015-12-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cong-Min FANG ,  Chih-Lin WANG ,  Kang-Min KUO

IPC: H01L27/088 ,  H01L21/3213 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/02 ,  H01L29/49

CPC classification number: H01L27/088 ,  H01L21/32139 ,  H01L21/823456 ,  H01L27/0207 ,  H01L29/4916 ,  H01L29/66545

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first source region, a second source region, a first drain region, and a second drain region. The semiconductor device structure includes a first gate structure over the substrate and between the first source region and the first drain region. The semiconductor device structure includes a second gate structure over the substrate and between the second source region and the second drain region. A first thickness of the first gate structure is greater than a second thickness of the second gate structure. A first gate width of the first gate structure is less than a second gate width of the second gate structure.

公开(公告)号：US20170110555A1

公开(公告)日：2017-04-20

申请号：US15369460

申请日：2016-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei LIAN ,  Chih-Lin WANG ,  Kang-Min KUO ,  Chih-Wei LIN

IPC: H01L29/51 ,  H01L21/28

CPC classification number: H01L29/517 ,  H01L21/28158 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, an interfacial layer formed over the substrate, and an insertion layer formed over the interfacial layer. The semiconductor structure further includes a gate dielectric layer formed over the insertion layer and a gate structure formed over the gate dielectric layer. The insertion layer and the gate dielectric layer may be metal oxides where the insertion layer has an oxygen coordination number greater than the gate dielectric layer.

公开(公告)号：US20160307896A1

公开(公告)日：2016-10-20

申请号：US14689859

申请日：2015-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Chih-Wei LIN ,  Chih-Lin WANG ,  Kang-Min KUO ,  Cheng-Wei LIAN

IPC: H01L27/092 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/40

CPC classification number: H01L27/092 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/823842 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The gate structure includes a gate dielectric layer formed over the substrate and a capping layer formed over the gate dielectric layer. The gate structure further includes a capping oxide layer formed over the capping layer and a work function metal layer formed over the capping oxide layer. The gate structure further includes a gate electrode layer formed over the work function metal layer.

Abstract translation: 提供半导体结构及其形成方法。 半导体结构包括衬底和形成在衬底上的栅极结构。 栅极结构包括形成在衬底上的栅极电介质层和形成在栅极介电层上的覆盖层。 栅极结构还包括形成在覆盖层上的覆盖氧化物层和形成在封盖氧化物层上的功函数金属层。 栅极结构还包括形成在功函数金属层上的栅电极层。

公开(公告)号：US20160190318A1

公开(公告)日：2016-06-30

申请号：US14800899

申请日：2015-07-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hsin CHEN ,  Chih-Lin WANG ,  Kang-Min KUO

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L27/088 ,  H01L29/0657 ,  H01L29/66492 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7835 ,  H01L29/7836

Abstract: A semiconductor device includes a substrate, first strain-inducing source and drain structures, a first gate structure, a first channel region, second strain-inducing source and drain structures, a second gate structure, and a second channel region. At least one of the first strain-inducing source and drain structures has a first proximity to the first channel region. At least one of the second strain-inducing source and drain structures has a second proximity to the second channel region. The second proximity is different from the first proximity.

Abstract translation: 半导体器件包括衬底，第一应变诱发源极和漏极结构，第一栅极结构，第一沟道区，第二应变诱发源和漏极结构，第二栅极结构和第二沟道区。 第一应变诱导源极和漏极结构中的至少一个具有与第一沟道区第一接近。 第二应变诱导源极和漏极结构中的至少一个具有与第二沟道区第二接近。 第二接近度与第一接近度不同。