公开(公告)号：US20230343649A1

公开(公告)日：2023-10-26

申请号：US18343322

申请日：2023-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Lun Chen ,  Chao-Hsien Huang ,  Li-Te Lin ,  Chun-Hsiung Lin

IPC: H01L21/8234 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L21/823468 ,  H01L29/515 ,  H01L29/785 ,  H01L29/66553 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6653 ,  H01L21/823864

Abstract: A method includes forming a gate stack over a semiconductor region, and forming a first gate spacer on a sidewall of the gate stack. The first gate spacer includes an inner sidewall spacer, and a dummy spacer portion on an outer side of the inner sidewall spacer. The method further includes removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. The air gap and the inner sidewall spacer in combination form a second gate spacer. A source/drain region is formed to have a portion on an outer side of the second gate spacer.

公开(公告)号：US11769822B2

公开(公告)日：2023-09-26

申请号：US17411704

申请日：2021-08-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Hao Chang ,  Li-Te Lin

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L29/66795 ,  H01L21/31116 ,  H01L21/32136 ,  H01L29/401 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor device includes a substrate, a semiconductor fin, gate spacers, a gate structure. The semiconductor fin is on the substrate. The gate spacers are over the semiconductor fin. The gate structure is on the semiconductor fin and between the gate spacers. The gate structure includes a gate dielectric layer and a first work function metal over the gate dielectric layer, in which a top surface of the first work function metal is lower than a top surface of the gate dielectric layer, and a distance between the top surface of the first work function metal and the top surface of the gate dielectric layer is less than about 1 nm.

公开(公告)号：US20230282520A1

公开(公告)日：2023-09-07

申请号：US18313783

申请日：2023-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Yi-Ruei Jhan ,  Fang-Wei Lee ,  Tze-Chung Lin ,  Chao-Hsien Huang ,  Li-Te Lin ,  Pinyen Lin ,  Akira Mineji

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/265 ,  H01L21/764 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/823431 ,  H01L27/0886 ,  H01L21/26586 ,  H01L21/823481 ,  H01L21/764 ,  H01L21/31053 ,  H01L21/02164 ,  H01L21/31116 ,  H01L21/0228

Abstract: A semiconductor device includes a substrate, a semiconductor fin protruding from the substrate, an isolation layer disposed above the substrate, a dielectric fin with a bottom portion embedded in the isolation layer, and a gate structure over top and sidewall surfaces of the semiconductor fin and the dielectric fin. The semiconductor fin has a first sidewall and a second sidewall facing away from the first sidewall. The isolation layer includes a first portion disposed on the first sidewall of the semiconductor fin and a second portion disposed on the second sidewall of the semiconductor fin. A top portion of the dielectric fin includes an air pocket with a top opening sealed by the gate structure.

公开(公告)号：US11646234B2

公开(公告)日：2023-05-09

申请号：US17362025

申请日：2021-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Yi-Ruei Jhan ,  Fang-Wei Lee ,  Tze-Chung Lin ,  Chao-Hsien Huang ,  Li-Te Lin ,  Pinyen Lin ,  Akira Mineji

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/265 ,  H01L21/764 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/823431 ,  H01L21/0228 ,  H01L21/02164 ,  H01L21/26586 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/764 ,  H01L21/823481 ,  H01L27/0886

Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor fin protruding from the semiconductor substrate, and an isolation layer disposed above the semiconductor substrate. The isolation layer includes a first portion disposed on a first sidewall of the semiconductor fin and a second portion disposed on a second sidewall of the semiconductor fin. Top surfaces of the first and second portions of the isolation layer are leveled. The first portion of the isolation layer includes an air pocket. The semiconductor device also includes a dielectric fin with a bottom portion embedded in the second portion of the isolation layer.

公开(公告)号：US11626506B2

公开(公告)日：2023-04-11

申请号：US17306316

申请日：2021-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chin Chang ,  Wei-Hao Wu ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49

Abstract: A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.

公开(公告)号：US20220344486A1

公开(公告)日：2022-10-27

申请号：US17238968

申请日：2021-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chin CHANG ,  Ming-Huan Tsai ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The method can include forming a fin structure on a substrate, forming a source/drain (S/D) region on the fin structure, forming a gate structure on the fin structure adjacent to the S/D region, and forming a capping structure on the gate structure. The forming the capping structure includes forming a conductive cap on the gate structure, forming a cap liner on the conductive cap, and forming a carbon-based cap on the cap liner. The method further includes forming a first contact structure on the S/D region, forming an insulating cap on the first contact structure, and forming a second contact structure on the conductive cap.

公开(公告)号：US11145749B2

公开(公告)日：2021-10-12

申请号：US16229979

申请日：2018-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen Lo ,  Yu-Lien Huang ,  Li-Te Lin

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L29/423 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/04 ,  H01L29/45

Abstract: A method for fabricating a semiconductor device includes forming a gate electrode structure over a first region of a semiconductor substrate, and selectively forming an oxide layer overlying the gate electrode structure by reacting a halide compound with oxygen to increase a height of the gate electrode structure. The halide compound may be silicon tetrachloride, and the oxide layer may be silicon dioxide. The gate electrode structure may be a dummy gate electrode, which is subsequently removed, and replaced with another gate electrode structure.

公开(公告)号：US11056393B2

公开(公告)日：2021-07-06

申请号：US16298720

申请日：2019-03-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Yi-Ruei Jhan ,  Fang-Wei Lee ,  Tze-Chung Lin ,  Chao-Hsien Huang ,  Li-Te Lin ,  Pinyen Lin ,  Akira Mineji

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/265 ,  H01L21/764 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/311

Abstract: A method for FinFET fabrication includes forming at least three semiconductor fins over a substrate, wherein first, second, and third of the semiconductor fins are lengthwise substantially parallel to each other, spacing between the first and second semiconductor fins is smaller than spacing between the second and third semiconductor fins; depositing a first dielectric layer over top and sidewalls of the semiconductor fins, resulting in a trench between the second and third semiconductor fins, bottom and two opposing sidewalls of the trench being the first dielectric layer; implanting ions into one of the two opposing sidewalls of the trench by a first tilted ion implantation process; implanting ions into another one of the two opposing sidewalls of the trench by a second tilted ion implantation process; depositing a second dielectric layer into the trench, the first and second dielectric layers having different materials; and etching the first dielectric layer.

公开(公告)号：US20210202712A1

公开(公告)日：2021-07-01

申请号：US17201342

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Lun Chen ,  Chao-Hsien Huang ,  Li-Te Lin ,  Chun-Hsiung Lin

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238

Abstract: A method includes forming a gate stack over a semiconductor region, and forming a first gate spacer on a sidewall of the gate stack. The first gate spacer includes an inner sidewall spacer, and a dummy spacer portion on an outer side of the inner sidewall spacer. The method further includes removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. The air gap and the inner sidewall spacer in combination form a second gate spacer. A source/drain region is formed to have a portion on an outer side of the second gate spacer.

公开(公告)号：US11043381B2

公开(公告)日：2021-06-22

申请号：US16258656

申请日：2019-01-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chin Chang ,  Li-Te Lin ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Pinyen Lin ,  Yu-Tien Shen ,  Ya-Wen Yeh

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/02

Abstract: A directional patterning method includes following steps. A substrate is provided with a mask layer thereon, and the mask layer has at least one opening pattern therein. A cyclic deposition and etching process is performed to increase a length of the at least one opening pattern.