公开(公告)号：US20210202436A1

公开(公告)日：2021-07-01

申请号：US16888868

申请日：2020-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kung-Chen Yeh ,  Szu-Wei Lu ,  Tsung-Fu Tsai ,  Ying-Ching Shih

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L21/56 ,  H01L21/78 ,  H01L25/065 ,  H01L21/268 ,  H01L21/304

Abstract: A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion.

公开(公告)号：US20210098421A1

公开(公告)日：2021-04-01

申请号：US16805865

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/768

Abstract: A package component for carrying a device package and an insulating layer thereon includes a molding layer, first and second redistribution structures disposed on two opposite sides of the molding layer, a semiconductor die, and a through interlayer via (TIV). A hardness of the molding layer is greater than that of the insulating layer that covers the device package. The device package is mounted on the second redistribution structure, and the insulating layer is disposed on the second redistribution structure opposite to the molding layer. The semiconductor die is embedded in the molding layer and electrically coupled to the device package through the second redistribution structure. The TIV penetrates through the molding layer to connect the first and the second redistribution structure. An electronic device and a manufacturing method thereof are also provided.

公开(公告)号：US20210098382A1

公开(公告)日：2021-04-01

申请号：US16927992

申请日：2020-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ting Lin ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Szu-Wei Lu

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: A package structure includes a plurality of semiconductor dies, an insulating encapsulant, a redistribution layer and a plurality of connecting elements. The insulating encapsulant is encapsulating the plurality of semiconductor dies. The redistribution layer is disposed on the insulating encapsulant in a build-up direction and electrically connected to the plurality of semiconductor dies, wherein the redistribution layer includes a plurality of conductive lines, a plurality of conductive vias and a plurality of dielectric layers alternately stacked, and a lateral dimension of the plurality of conductive vias increases along the build-up direction. The connecting elements are disposed in between the redistribution layer and the semiconductor dies, wherein the connecting elements includes a body portion joined with the semiconductor dies and a via portion joined with the redistribution layer, wherein a lateral dimension of the via portion decreases along the build-up direction.

公开(公告)号：US20210082894A1

公开(公告)日：2021-03-18

申请号：US16572619

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Weiming Chris Chen ,  Chi-Hsi Wu ,  Chih-Wei Wu ,  Kuo-Chiang Ting ,  Szu-Wei Lu ,  Shang-Yun Hou ,  Ying-Ching Shih ,  Hsien-Ju Tsou ,  Cheng-Chieh Li

IPC: H01L25/18 ,  H01L23/367 ,  H01L25/00 ,  H01L23/00 ,  H01L21/82 ,  H01L23/48 ,  H01L21/56

Abstract: A package structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipating element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipating element connects to the first semiconductor die, and the first semiconductor die is between the circuit element and the heat dissipating element, where a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipating element is substantially equal to a second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die and the heat dissipating element, wherein a surface of the heat dissipating element is substantially leveled with the insulating encapsulation.

公开(公告)号：US20210066151A1

公开(公告)日：2021-03-04

申请号：US16846400

申请日：2020-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Pin Hu ,  Chin-Fu Kao ,  Li-Hui Cheng ,  Szu-Wei Lu ,  Wen-Hsin Wei ,  Chih-Chien Pan

IPC: H01L23/31 ,  H01L29/78 ,  H01L23/498 ,  H01L27/06

Abstract: A package structure includes a circuit substrate, a semiconductor package, a lid structure, a passive device and a barrier structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The lid structure is disposed on the circuit substrate covering the semiconductor package. The lid structure is attached to the circuit substrate through an adhesive material. The passive device is disposed on the circuit substrate in between the semiconductor package and the lid structure. The barrier structure is separating the passive device from the lid structure and the adhesive material, and the barrier structure is in contact with the adhesive material.

公开(公告)号：US20210057383A1

公开(公告)日：2021-02-25

申请号：US17094161

申请日：2020-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Wei Lu ,  Ying-Da Wang ,  Li-Chung Kuo ,  Jing-Cheng Lin

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/78

Abstract: A method includes bonding a first and a second package component on a top surface of a third package component, and dispensing a polymer. The polymer includes a first portion in a space between the first and the third package components, a second portion in a space between the second and the third package components, and a third portion in a gap between the first and the second package components. A curing step is then performed on the polymer. After the curing step, the third portion of the polymer is sawed to form a trench between the first and the second package components.

公开(公告)号：US20210020534A1

公开(公告)日：2021-01-21

申请号：US17063143

申请日：2020-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chien Pan ,  Chin-Fu Kao ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00

Abstract: A method of forming a semiconductor device includes attaching a first semiconductor device to a first surface of a substrate; forming a sacrificial structure on the first surface of the substrate around the first semiconductor device, the sacrificial structure encircling a first region of the first surface of the substrate; and forming an underfill material in the first region.

公开(公告)号：US10852476B2

公开(公告)日：2020-12-01

申请号：US16285234

申请日：2019-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao Chen ,  Chin-Fu Kao ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC: G02B6/12 ,  G02B6/43 ,  G02B6/30 ,  G02B6/122

Abstract: A semiconductor package includes a photonic integrated circuit, an encapsulating material, and a redistribution structure. The photonic integrated circuit includes a coupling surface, a back surface opposite to the coupling surface and a plurality of optical couplers disposed on the coupling surface and configured to be coupled to a plurality of optical fibers. The encapsulating material encapsulates the photonic integrated circuit and revealing the plurality of optical couplers. The redistribution structure is disposed over the encapsulating material and the back surface of the photonic integrated circuit, wherein the redistribution structure is electrically connected to the photonic integrated circuit.

公开(公告)号：US10756058B2

公开(公告)日：2020-08-25

申请号：US16116892

申请日：2018-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Ching Shih ,  Chih-Wei Wu ,  Szu-Wei Lu

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L21/56

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first chip, a second chip, self-aligned structures, a bridge structure, and an insulating encapsulant. The first chip has a first rear surface opposite to a first active surface. The second chip is disposed beside the first chip and has a second rear surface opposite to a second active surface. The self-aligned structures are disposed on the first rear surface of the first chip and the second rear surface of the second chip. The bridge structure is electrically connected to the first chip and the second chip. The insulating encapsulant covers at least the side surfaces of the first and second chips, a side surface of the semiconductor substrate, and the side surfaces of the self-aligned structures.

公开(公告)号：US20200176337A1

公开(公告)日：2020-06-04

申请号：US16420186

申请日：2019-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chao Mao ,  Chin-Chuan Chang ,  Szu-Wei Lu

IPC: H01L21/66 ,  H01L21/56 ,  H01L21/306

Abstract: An apparatus for detecting an endpoint of a grinding process includes a connecting device, a timer and a controller. The connecting device is connected to a sensor that periodically senses an interface of a reconstructed wafer comprising a plurality of dies of at least two types to generate a thickness signal comprising thicknesses from a surface of an insulating layer of the reconstructed wafer to the interface of the reconstructed wafer. The timer is configured to generate a clock signal having a plurality of pulses with a time interval. The controller is coupled to the sensor and the timer, and configured to filter the thickness signal according to the clock signal to output a thickness extremum among the thicknesses in the thickness signal within each time interval, wherein the thickness signal after the filtering is used to determine the endpoint of the grinding process being performed on the reconstructed wafer.