公开(公告)号：US09159735B2

公开(公告)日：2015-10-13

申请号：US13945002

申请日：2013-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yong-Shiuan Tsair ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yu-Ling Hsu ,  Tsun-Kai Tsao ,  Ming-Huei Shen

IPC: H01L27/115 ,  H01L29/788 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L27/11517 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/7885

Abstract: Some embodiments of the present disclosure relates to an architecture to create split gate flash memory cell that has lower common source (CS) resistance and a reduced cell size by utilizing a buried conductive common source structure. A two-step etch process is carried out to create a recessed path between two split gate flash memory cells. A single ion implantation to form the common source also forms a conductive path beneath the STI region that connects two split gate flash memory cells and provide potential coupling during programming and erasing and thus electrically connect the common sources of memory cells along a direction that forms a CS line. The architecture contains no OD along the source line between the cells, thus eliminating the effects of CS rounding and CS resistance, resulting in a reduced space between cells in an array. Hence, this particular architecture reduces the resistance and the buried conductive path between several cells in an array suppresses the area over head.

Abstract translation: 本公开的一些实施例涉及通过利用埋入式导电公共源结构来创建具有较低共同源（CS）电阻和减小的单元尺寸的分离栅极闪存单元的架构。 执行两步蚀刻工艺以在两个分离栅极闪存单元之间形成凹陷路径。 用于形成公共源的单个离子注入还在STI区域下方形成连接两个分离栅极快速存储器单元的导电路径，并且在编程和擦除期间提供电位耦合，从而沿共同的方向电连接存储器单元的方向 CS线。 该架构沿单元格之间的源极线不包含OD，从而消除CS舍入和CS电阻的影响，导致阵列中单元之间的空间减小。 因此，这种特定的结构降低了电阻，并且阵列中的几个单元之间的掩埋导电路径抑制了头上的区域。

公开(公告)号：US20140264534A1

公开(公告)日：2014-09-18

申请号：US13891281

申请日：2013-05-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yong-Shiuan Tsair ,  Wen-Ting Chu ,  Po-Wei Liu ,  Wen-Tuo Huang

IPC: H01L29/788 ,  H01L29/66

CPC classification number: H01L29/66825 ,  H01L27/11517

Abstract: Some embodiments of the present disclosure relates to an architecture to create split gate flash memory cell that has lower common source (CS) resistance and a reduced cell size by utilizing isolated source regions that are diffused only in the active regions between the stacked control gate structures. The architecture contains no CS under the isolation region, thus eliminating the effects of CS rounding and CS resistance, resulting in a reduced space between cells in an array. A metal layer is disposed along the semiconductor body above the common source regions to provide potential coupling during programming and erasing and thus electrically connect the common sources of memory cells along a direction that forms a CS line. Hence, this particular architecture reduces the resistance and the metal connection over several cells in an array suppresses the area over head.

Abstract translation: 本公开的一些实施例涉及通过利用仅在堆叠的控制栅极结构之间的有源区域中扩散的隔离源极区域来创建具有较低公共源（CS）电阻和降低的单元尺寸的分离栅极闪存单元的架构 。 该架构在隔离区域内不包含CS，从而消除CS舍入和CS电阻的影响，导致阵列中的单元之间的空间减小。 金属层沿共同源极区域上方的半导体本体设置，以在编程和擦除期间提供电位耦合，从而沿着形成CS线的方向电连接存储器单元的公共源。 因此，这种特定的架构降低了电阻，并且阵列中的几个单元的金属连接抑制了磁头上的区域。

公开(公告)号：US11456293B2

公开(公告)日：2022-09-27

申请号：US16549077

申请日：2019-08-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Wen-Tuo Huang ,  Yong-Shiuan Tsair

IPC: H01L27/06 ,  H01L21/8234

Abstract: The present disclosure describes a method for forming polysilicon resistors with high-k dielectrics and polysilicon gate electrodes. The method includes depositing a resistor stack on a substrate having spaced apart first and second isolation regions. Further the method includes patterning the resistor stack to form a polysilicon resistor structure on the first isolation region and a gate structure between the first and second isolation regions, and doping the polysilicon resistor structure to form a doped layer in the polysilicon layer of the polysilicon resistor structure and source-drain regions in the substrate adjacent to the gate structure. Also, the method includes replacing the polysilicon layer in the gate structure with a metal gate electrode to form a transistor structure.

公开(公告)号：US11158377B2

公开(公告)日：2021-10-26

申请号：US16952411

申请日：2020-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Kuang Yang ,  Ping-Cheng Li ,  Hung-Ling Shih ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yu-Ling Hsu ,  Yong-Shiuan Tsair ,  Chia-Sheng Lin

IPC: G11C16/08 ,  H01L27/108 ,  G11C11/16 ,  H01L27/11521

Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.

公开(公告)号：US10943913B2

公开(公告)日：2021-03-09

申请号：US16364405

申请日：2019-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Tuo Huang ,  Ping-Cheng Li ,  Hung-Ling Shih ,  Po-Wei Liu ,  Yu-Ling Hsu ,  Yong-Shiuan Tsair ,  Chia-Sheng Lin ,  Shih Kuang Yang

IPC: H01L27/11521 ,  H01L23/528 ,  H01L23/532 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40 ,  H01L21/768 ,  H01L23/522 ,  H01L29/788 ,  H01L21/28

Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

公开(公告)号：US10680002B2

公开(公告)日：2020-06-09

申请号：US15981056

申请日：2018-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Ling Shih ,  Chieh-Fei Chiu ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yu-Ling Hsu ,  Yong-Shiuan Tsair ,  Shih Kuang Yang

IPC: H01L21/311 ,  H01L27/11521 ,  H01L29/788 ,  H01L21/308 ,  H01L21/768 ,  H01L21/027 ,  H01L21/762 ,  H01L21/28

Abstract: In some embodiments, a method for forming a semiconductor device is provided. The method includes forming a pad stack over a semiconductor substrate, where the pad stack includes a lower pad layer and an upper pad layer. An isolation structure having a pair of isolation segments separated in a first direction by the pad stack is formed in the semiconductor substrate. The upper pad is removed to form an opening, where the isolation segments respectively have opposing sidewalls in the opening that slant at a first angle. A first etch is performed that partially removes the lower pad layer and isolation segments in the opening so the opposing sidewalls slant at a second angle greater than the first angle. A second etch is performed to round the opposing sidewalls and remove the lower pad layer from the opening. A floating gate is formed in the opening.

公开(公告)号：US09252150B1

公开(公告)日：2016-02-02

申请号：US14445697

申请日：2014-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Ling Shih ,  Yong-Shiuan Tsair ,  Tsun-Kai Tsao ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yu-Ling Hsu

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L21/027 ,  H01L21/28 ,  H01L21/762 ,  H01L21/321

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66825

Abstract: The present disclosure relates to a non-volatile memory cell structure, and an associated method. A non-volatile memory cell includes two transistors spaced apart from one another with floating gates connected together by a floating gate bridge. During the operation, the non-volatile memory cell is programmed and erased from one first transistor and read from the other second transistor. Since the floating gates of the two transistors are connected together and insulated from other ambient layers, stored charges can be controlled from the first transistor and affect a threshold of the second transistor.

Abstract translation: 本公开涉及非易失性存储器单元结构以及相关联的方法。 非易失性存储单元包括两个彼此间隔开的晶体管，浮置栅极通过浮栅连接在一起。 在操作期间，非易失性存储单元被编程并从一个第一晶体管擦除并从另一个第二晶体管读取。 由于两个晶体管的浮置栅极连接在一起并与其他环境层绝缘，所以可以从第一晶体管控制存储的电荷并影响第二晶体管的阈值。

公开(公告)号：US11552087B2

公开(公告)日：2023-01-10

申请号：US17190678

申请日：2021-03-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Tuo Huang ,  Ping-Cheng Li ,  Hung-Ling Shih ,  Po-Wei Liu ,  Yu-Ling Hsu ,  Yong-Shiuan Tsair ,  Chia-Sheng Lin ,  Shih Kuang Yang

IPC: H01L27/11521 ,  H01L23/528 ,  H01L23/532 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40 ,  H01L21/768 ,  H01L23/522 ,  H01L29/788 ,  H01L21/28

Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

公开(公告)号：US20220359497A1

公开(公告)日：2022-11-10

申请号：US17870415

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Wen-Tuo Huang ,  Yong-Shiuan Tsair

IPC: H01L27/06 ,  H01L21/8234

Abstract: The present disclosure describes a method for forming polysilicon resistors with high-k dielectrics and polysilicon gate electrodes. The method includes depositing a resistor stack on a substrate having spaced apart first and second isolation regions. Further the method includes patterning the resistor stack to form a polysilicon resistor structure on the first isolation region and a gate structure between the first and second isolation regions, and doping the polysilicon resistor structure to form a doped layer in the polysilicon layer of the polysilicon resistor structure and source-drain regions in the substrate adjacent to the gate structure. Also, the method includes replacing the polysilicon layer in the gate structure with a metal gate electrode to form a transistor structure.

公开(公告)号：US11189627B2

公开(公告)日：2021-11-30

申请号：US16822315

申请日：2020-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Ling Shih ,  Chieh-Fei Chiu ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yu-Ling Hsu ,  Yong-Shiuan Tsair ,  Shih Kuang Yang

IPC: H01L29/778 ,  H01L27/11521 ,  H01L29/788 ,  H01L21/308 ,  H01L21/768 ,  H01L21/027 ,  H01L21/762 ,  H01L21/28

Abstract: In some embodiments, a method for forming a semiconductor device is provided. The method includes forming a pad stack over a semiconductor substrate, where the pad stack includes a lower pad layer and an upper pad layer. An isolation structure having a pair of isolation segments separated in a first direction by the pad stack is formed in the semiconductor substrate. The upper pad is removed to form an opening, where the isolation segments respectively have opposing sidewalls in the opening that slant at a first angle. A first etch is performed that partially removes the lower pad layer and isolation segments in the opening so the opposing sidewalls slant at a second angle greater than the first angle. A second etch is performed to round the opposing sidewalls and remove the lower pad layer from the opening. A floating gate is formed in the opening.