公开(公告)号：US20240365560A1

公开(公告)日：2024-10-31

申请号：US18768265

申请日：2024-07-10

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Mauricio Manfrini ,  Bo-Feng Young ,  Chun-Chieh Li ,  Han-Jong Chia ,  Sai-Hooi Yeong

IPC分类号： H10B51/30 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC分类号： H10B51/30 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391

摘要： A ferroelectric tunnel junction (FTJ) memory device includes a bottom electrode located over a substrate, a top electrode overlying the bottom electrode, and a ferroelectric tunnel junction memory element located between the bottom electrode and the top electrode. The ferroelectric tunnel junction memory element includes at least one ferroelectric material layer and at least one tunneling dielectric layer.

公开(公告)号：US12120885B2

公开(公告)日：2024-10-15

申请号：US18354858

申请日：2023-07-19

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Mauricio Manfrini ,  Bo-Feng Young ,  Chun-Chieh Li ,  Han-Jong Chia ,  Sai-Hooi Yeong

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H10B51/30

CPC分类号： H10B51/30 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391

摘要： A ferroelectric tunnel junction (FTJ) memory device includes a bottom electrode located over a substrate, a top electrode overlying the bottom electrode, and a ferroelectric tunnel junction memory element located between the bottom electrode and the top electrode. The ferroelectric tunnel junction memory element includes at least one ferroelectric material layer and at least one tunneling dielectric layer.

公开(公告)号：US11817485B2

公开(公告)日：2023-11-14

申请号：US17227460

申请日：2021-04-12

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Hung Wei Li ,  Mauricio Manfrini ,  Sai-Hooi Yeong ,  Yu-Ming Lin

IPC分类号： H01L21/00 ,  H01L29/00 ,  H01L27/00 ,  H01L29/417 ,  H01L29/786 ,  H01L21/768 ,  H01L29/40 ,  H01L29/66

CPC分类号： H01L29/41733 ,  H01L21/76802 ,  H01L21/76877 ,  H01L29/401 ,  H01L29/66969 ,  H01L29/7869

摘要： Field effect transistors and method of making. The field effect transistors include a pair of active regions in a channel layer, a channel region located between the pair of active regions and a self-aligned passivation layer located on a surface of the pair of active regions.

公开(公告)号：US11757047B2

公开(公告)日：2023-09-12

申请号：US17216747

申请日：2021-03-30

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Yong-Jie Wu ,  Yen-Chung Ho ,  Hui-Hsien Wei ,  Chia-Jung Yu ,  Pin-Cheng Hsu ,  Mauricio Manfrini ,  Chung-Te Lin

IPC分类号： H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L29/40

CPC分类号： H01L29/78696 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/7869 ,  H01L29/78618

摘要： A semiconductor device includes a first dielectric layer, a gate electrode embedded within the first dielectric layer, a layer stack including a gate dielectric layer, a channel layer including a semiconducting metal oxide material, and a second dielectric layer, and a source electrode and a drain electrode embedded in the second dielectric layer and contacting a respective portion of a top surface of the channel layer. A combination of the gate electrode, the gate dielectric layer, the channel layer, the source electrode, and the drain electrode forms a transistor. The total length of the periphery of a bottom surface of the channel layer that overlies the gate electrode is equal to the width of the gate electrode or twice the width of the gate electrode, and resputtering of the gate electrode material on sidewalls of the channel layer is minimized.

公开(公告)号：US11737288B2

公开(公告)日：2023-08-22

申请号：US17222123

申请日：2021-04-05

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Yen-Chung Ho ,  Yong-Jie Wu ,  Chia-Jung Yu ,  Hui-Hsien Wei ,  Mauricio Manfrini ,  Ken-Ichi Goto ,  Pin-Cheng Hsu

IPC分类号： H10B63/00 ,  H10B53/30 ,  H10B61/00

CPC分类号： H10B63/30 ,  H10B53/30 ,  H10B61/22

摘要： A memory device and method of making the same, the memory device including bit lines disposed on the substrate; memory cells disposed on the bit lines; a first dielectric layer disposed on the substrate, surrounding the bit lines and the memory cells; a second dielectric layer disposed on the first dielectric layer; thin film transistors (TFTs) embedded in the second dielectric layer and configured to selectively provide electric power to corresponding memory cells, the TFTs comprising drain lines disposed on the memory cells, source lines disposed on the first dielectric layer, and selector layers electrically connected to the source lines and the drain lines; and word lines disposed on the second dielectric layer and electrically connected to the TFTs.

公开(公告)号：US20230029955A1

公开(公告)日：2023-02-02

申请号：US17738169

申请日：2022-05-06

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Neil Quinn Murray ,  Mauricio Manfrini

IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L29/51 ,  H01L29/45

摘要： Disclosed transistor structures include a gate electrode, an active layer, a gate dielectric layer separating the active layer from the gate electrode, a source electrode, a drain electrode, and a hydrogen-rich material layer separating the source electrode and the drain electrode from the active layer. The presence of hydrogen in the hydrogen-rich material layer may act to reduce contact resistances and Schottky barriers between the source electrode and the active layer, and between the drain electrode and the active layer, thus leading to improved device performance. The disclosed transistor structures may be formed in a BEOL process and may be incorporated with other BEOL circuit components. As such, the disclosed transistor structures may include materials that may be processed at low temperatures and thus, may not damage previously fabricated devices.

公开(公告)号：US20220246767A1

公开(公告)日：2022-08-04

申请号：US17467478

申请日：2021-09-07

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Neil MURRAY ,  Hung-Wei Li ,  Mauricio Manfrini

IPC分类号： H01L29/786 ,  H01L21/02 ,  H01L29/66

摘要： A thin film transistor includes an insulating matrix layer including an opening therein, a hydrogen-blocking dielectric barrier layer continuously extending over a bottom surface and sidewalls of the opening and over a top surface of the insulating matrix layer, a gate electrode located within the opening, a stack of a gate dielectric and a semiconducting metal oxide plate overlying the gate electrode and horizontally-extending portions of the hydrogen-blocking dielectric barrier layer that overlie the insulating matrix layer, and a source electrode and a drain electrode contacting a respective portion of a top surface of the semiconducting metal oxide plate.

公开(公告)号：US12057471B2

公开(公告)日：2024-08-06

申请号：US18354573

申请日：2023-07-18

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Han-Jong Chia ,  Mauricio Manfrini

IPC分类号： H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L49/02 ,  H10B51/30 ,  H10B53/30

CPC分类号： H01L28/56 ,  H01L21/02601 ,  H01L28/60 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7851 ,  H01L29/78696 ,  H10B51/30 ,  H10B53/30

摘要： A memory device, transistor, and methods of making the same, the memory device including a memory cell including: a bottom electrode layer; a high-k dielectric layer disposed on the bottom electrode layer; a discontinuous seed structure comprising discrete particles of a metal disposed on the high-k dielectric layer; a ferroelectric (FE) layer disposed on the seed structure and directly contacting portions of high-k dielectric layer exposed through the seed structure; and a top electrode layer disposed on the FE layer.

公开(公告)号：US20240136440A1

公开(公告)日：2024-04-25

申请号：US18401395

申请日：2023-12-30

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Hung-Wei Li ,  Yu-Ming Lin ,  Mauricio Manfrini ,  Sai-Hooi Yeong

IPC分类号： H01L29/786 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H10B51/30 ,  H10B51/40 ,  H10B61/00 ,  H10B63/00

CPC分类号： H01L29/78618 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/78642 ,  H01L29/7869 ,  H01L29/78696 ,  H10B51/30 ,  H10B51/40 ,  H10B61/22 ,  H10B63/34 ,  H10B63/80

摘要： A thin film transistor and method of making the same, the thin film transistor including: a substrate; a word line disposed on the substrate; a semiconductor layer disposed on the substrate, the semiconductor layer having a source region, a drain region, and a channel region disposed between the source and drain regions and overlapping with the word line in a vertical direction perpendicular to a plane of the substrate; a hydrogen diffusion barrier layer overlapping with the channel region in the vertical direction; a gate dielectric layer disposed between the channel region and the word line; and source and drain electrodes respectively electrically coupled to the source and drain regions.

公开(公告)号：US20230361221A1

公开(公告)日：2023-11-09

申请号：US18354681

申请日：2023-07-19

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Yong-Jie Wu ,  Hui-Hsien Wei ,  Yen-Chung Ho ,  Mauricio Manfrini ,  Chia-Jung Yu ,  Chung-Te Lin ,  Pin-Cheng Hsu

IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423

CPC分类号： H01L29/78696 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/66742 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/42364

摘要： A semiconductor device includes a first dielectric layer, a gate electrode embedded within the first dielectric layer, a layer stack including a gate dielectric layer, a channel layer including a semiconducting metal oxide material, and a second dielectric layer, and a source electrode and a drain electrode embedded in the second dielectric layer and contacting a respective portion of a top surface of the channel layer. A combination of the gate electrode, the gate dielectric layer, the channel layer, the source electrode, and the drain electrode forms a transistor. The total length of the periphery of a bottom surface of the channel layer that overlies the gate electrode is equal to the width of the gate electrode or twice the width of the gate electrode, and resputtering of the gate electrode material on sidewalls of the channel layer is minimized.