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1.发明授权公开(公告)号：US12125921B2
公开(公告)日：2024-10-22
申请号：US18354681
申请日：2023-07-19
发明人： Yong-Jie Wu , Hui-Hsien Wei , Yen-Chung Ho , Mauricio Manfrini , Chia-Jung Yu , Chung-Te Lin , Pin-Cheng Hsu
IPC分类号： H01L29/786 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/66
CPC分类号： H01L29/78696 , H01L29/401 , H01L29/41733 , H01L29/41775 , H01L29/42364 , H01L29/42384 , H01L29/66742 , H01L29/78618 , H01L29/7869
摘要： A semiconductor device includes a first dielectric layer, a gate electrode embedded within the first dielectric layer, a layer stack including a gate dielectric layer, a channel layer including a semiconducting metal oxide material, and a second dielectric layer, and a source electrode and a drain electrode embedded in the second dielectric layer and contacting a respective portion of a top surface of the channel layer. A combination of the gate electrode, the gate dielectric layer, the channel layer, the source electrode, and the drain electrode forms a transistor. The total length of the periphery of a bottom surface of the channel layer that overlies the gate electrode is equal to the width of the gate electrode or twice the width of the gate electrode, and resputtering of the gate electrode material on sidewalls of the channel layer is minimized.
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公开(公告)号：US11923459B2
公开(公告)日：2024-03-05
申请号：US17228534
申请日：2021-04-12
发明人： Hung Wei Li , Mauricio Manfrini , Sai-Hooi Yeong , Yu-Ming Lin
IPC分类号： H01L29/786 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/66 , H10B51/30 , H10B51/40 , H10B61/00 , H10B63/00
CPC分类号： H01L29/78618 , H01L29/401 , H01L29/41733 , H01L29/41775 , H01L29/42384 , H01L29/66742 , H01L29/78642 , H01L29/7869 , H01L29/78696 , H10B51/30 , H10B51/40 , H10B61/22 , H10B63/34 , H10B63/80
摘要： A thin film transistor and method of making the same, the thin film transistor including: a substrate; a word line disposed on the substrate; a semiconductor layer disposed on the substrate, the semiconductor layer having a source region, a drain region, and a channel region disposed between the source and drain regions and overlapping with the word line in a vertical direction perpendicular to a plane of the substrate; a hydrogen diffusion barrier layer overlapping with the channel region in the vertical direction; a gate dielectric layer disposed between the channel region and the word line; and source and drain electrodes respectively electrically coupled to the source and drain regions.
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公开(公告)号：US11805657B2
公开(公告)日：2023-10-31
申请号：US17229926
申请日：2021-04-14
CPC分类号： H10B51/30 , H01L29/40111 , H01L29/516 , H01L29/6684 , H01L29/78391
摘要： A ferroelectric tunnel junction (FTJ) memory device includes a bottom electrode located over a substrate, a top electrode overlying the bottom electrode, and a ferroelectric tunnel junction memory element located between the bottom electrode and the top electrode. The ferroelectric tunnel junction memory element includes at least one ferroelectric material layer and at least one tunneling dielectric layer.
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公开(公告)号：US11756987B2
公开(公告)日：2023-09-12
申请号：US17230477
申请日：2021-04-14
发明人： Han-Jong Chia , Mauricio Manfrini
IPC分类号： H01L29/51 , H01L29/78 , H01L29/66 , H01L29/786 , H01L21/28 , H10B53/30 , H01L21/02 , H01L49/02
CPC分类号： H01L28/56 , H01L21/02601 , H01L28/60 , H01L29/40111 , H01L29/516 , H01L29/6684 , H01L29/66742 , H01L29/66795 , H01L29/7851 , H01L29/78391 , H01L29/78696 , H10B53/30
摘要： A memory device, transistor, and methods of making the same, the memory device including a memory cell including: a bottom electrode layer; a high-k dielectric layer disposed on the bottom electrode layer; a discontinuous seed structure comprising discrete particles of a metal disposed on the high-k dielectric layer; a ferroelectric (FE) layer disposed on the seed structure and directly contacting portions of high-k dielectric layer exposed through the seed structure; and a top electrode layer disposed on the FE layer.
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5.发明授权公开(公告)号：US11696453B2
公开(公告)日：2023-07-04
申请号：US17843118
申请日：2022-06-17
发明人： Yong-Jie Wu , Yen-Chung Ho , Pin-Cheng Hsu , Mauricio Manfrini , Chung-Te Lin
CPC分类号： H10B63/34 , H01L29/66969 , H01L29/7869 , H01L29/78642 , H10B53/30 , H10B53/40 , H10B63/80 , H10N70/011 , H10N70/231 , H10N70/24
摘要： A device structure includes at least one selector device. Each selector device includes a vertical stack including, from bottom to top, a bottom electrode, a metal oxide semiconductor channel layer, and a top electrode and located over a substrate, a gate dielectric layer contacting sidewalls of the bottom electrode, the metal oxide semiconductor channel layer, and the top electrode, and a gate electrode formed within the gate dielectric layer and having a top surface that is coplanar with a top surface of the top electrode. Each top electrode or each bottom electrode of the at least one selector device may be contacted by a respective nonvolatile memory element to provide a one-selector one-resistor memory cell.
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公开(公告)号：US11569250B2
公开(公告)日：2023-01-31
申请号：US17230598
申请日：2021-04-14
发明人： Bo-Feng Young , Mauricio Manfrini , Sai-Hooi Yeong , Han-Jong Chia , Yu-Ming Lin
IPC分类号： H01L27/11 , G11C11/22 , H01L27/11507 , H01L29/786 , H01L21/02 , H01L29/66
摘要： A memory device includes metal interconnect structures embedded within dielectric material layers that overlie a top surface of a substrate, a thin film transistor embedded in a first dielectric material layer selected from the dielectric material layers, and is vertically spaced from the top surface of the substrate, and a ferroelectric memory cell embedded within the dielectric material layers. A first node of the ferroelectric memory cell is electrically connected to a node of the thin film transistor through a subset of the metal interconnect structures that is located above, and vertically spaced from, the top surface of the substrate.
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公开(公告)号：US12125920B2
公开(公告)日：2024-10-22
申请号：US18191567
申请日：2023-03-28
IPC分类号： H01L29/66 , H01L29/10 , H01L29/786
CPC分类号： H01L29/78696 , H01L29/1054 , H01L29/66765 , H01L29/66969 , H01L29/78669 , H01L29/78678 , H01L29/7869
摘要： A transistor device and method of making the same, the transistor device including: a substrate; a word line disposed on the substrate; a gate insulating layer disposed on the word line; a dual-layer semiconductor channel including: a first channel layer disposed on the gate insulating layer; and a second channel layer disposed on the first channel layer, such that the second channel layer contacts side and top surfaces of the first channel layer; and source and drain electrodes electrically coupled to the second channel layer. When a voltage is applied to the word line, the first channel layer has a first electrical resistance and the second channel layer has a second electrical resistance that is different from the first electrical resistance.
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8.发明公开公开(公告)号：US20240178322A1
公开(公告)日：2024-05-30
申请号：US18432574
申请日：2024-02-05
IPC分类号： H01L29/786 , H01L21/02 , H01L29/66
CPC分类号： H01L29/78606 , H01L21/02178 , H01L21/02565 , H01L29/66969 , H01L29/7869
摘要： A thin film transistor includes an insulating matrix layer including an opening therein, a hydrogen-blocking dielectric barrier layer continuously extending over a bottom surface and sidewalls of the opening and over a top surface of the insulating matrix layer, a gate electrode located within the opening, a stack of a gate dielectric and a semiconducting metal oxide plate overlying the gate electrode and horizontally-extending portions of the hydrogen-blocking dielectric barrier layer that overlie the insulating matrix layer, and a source electrode and a drain electrode contacting a respective portion of a top surface of the semiconducting metal oxide plate.
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公开(公告)号：US11942147B2
公开(公告)日：2024-03-26
申请号：US17872111
申请日：2022-07-25
发明人： Marcus Johannes Henricus Van Dal , Gerben Doornbos , Georgios Vellianitis , Blandine Duriez , Mauricio Manfrini
CPC分类号： G11C13/0007 , G11C13/0069 , H10B63/34 , H10B63/80 , H10N70/011 , H10N70/253 , H10N70/841 , H10N70/8833
摘要： A memory device is provided, which may include a first electrode, a memory layer stack including at least one semiconducting metal oxide layer and at least one hydrogen-containing metal layer, and a second electrode. A semiconductor device is provided, which may include a semiconducting metal oxide layer containing a source region, a drain region, and a channel region, a hydrogen-containing metal layer located on a surface of the channel region, and a gate electrode located on the hydrogen-containing metal layer. Each hydrogen-containing metal layer may include at least one metal selected from platinum, iridium, osmium, and ruthenium at an atomic percentage that is at least 90%, and may include hydrogen atoms at an atomic percentage in a range from 0.001% to 10%. Hydrogen atoms may be reversibly impregnated into a respective semiconducting metal oxide layer to change resistivity and to encode a memory bit.
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10.发明授权公开(公告)号：US11929436B2
公开(公告)日：2024-03-12
申请号：US17467478
申请日：2021-09-07
发明人： Neil Murray , Hung-Wei Li , Mauricio Manfrini
IPC分类号： H01L29/66 , H01L21/02 , H01L29/786
CPC分类号： H01L29/78606 , H01L21/02178 , H01L21/02565 , H01L29/66969 , H01L29/7869
摘要： A thin film transistor includes an insulating matrix layer including an opening therein, a hydrogen-blocking dielectric barrier layer continuously extending over a bottom surface and sidewalls of the opening and over a top surface of the insulating matrix layer, a gate electrode located within the opening, a stack of a gate dielectric and a semiconducting metal oxide plate overlying the gate electrode and horizontally-extending portions of the hydrogen-blocking dielectric barrier layer that overlie the insulating matrix layer, and a source electrode and a drain electrode contacting a respective portion of a top surface of the semiconducting metal oxide plate.
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