-
公开(公告)号：US12125920B2
公开(公告)日：2024-10-22
申请号：US18191567
申请日：2023-03-28
IPC分类号： H01L29/66 , H01L29/10 , H01L29/786
CPC分类号： H01L29/78696 , H01L29/1054 , H01L29/66765 , H01L29/66969 , H01L29/78669 , H01L29/78678 , H01L29/7869
摘要： A transistor device and method of making the same, the transistor device including: a substrate; a word line disposed on the substrate; a gate insulating layer disposed on the word line; a dual-layer semiconductor channel including: a first channel layer disposed on the gate insulating layer; and a second channel layer disposed on the first channel layer, such that the second channel layer contacts side and top surfaces of the first channel layer; and source and drain electrodes electrically coupled to the second channel layer. When a voltage is applied to the word line, the first channel layer has a first electrical resistance and the second channel layer has a second electrical resistance that is different from the first electrical resistance.
-
公开(公告)号：US12113115B2
公开(公告)日：2024-10-08
申请号：US17467497
申请日：2021-09-07
发明人： Wu-Wei Tsai , Chun-Chieh Lu , Hai-Ching Chen , Yu-Ming Lin , Sai-Hooi Yeong
IPC分类号： H01L29/24 , H01L21/02 , H01L21/443 , H01L29/49 , H01L29/66 , H01L29/786
CPC分类号： H01L29/4908 , H01L21/02233 , H01L21/02252 , H01L21/02255 , H01L21/02565 , H01L21/443 , H01L29/24 , H01L29/66969 , H01L29/7869
摘要： A thin film transistor may be manufactured by forming a gate electrode in an insulating layer over a substrate, forming a gate dielectric over the gate electrode and the insulating layer, forming an active layer over the gate electrode, and forming a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. A surface oxygen concentration may be increased in at least one of the gate dielectric and the active layer by introducing oxygen atoms into a surface region of a respective one of the gate dielectric and the active layer.
-
3.发明授权公开(公告)号：US12040409B2
公开(公告)日：2024-07-16
申请号：US17467492
申请日：2021-09-07
发明人： Wu-Wei Tsai , Hai-Ching Chen , Sai-Hooi Yeong , Yu-Ming Lin
IPC分类号： H01L29/66 , H01L23/528 , H01L27/12 , H01L29/786
CPC分类号： H01L29/7869 , H01L23/5283 , H01L27/1207 , H01L29/66772 , H01L29/78654
摘要： A semiconductor device includes an insulating layer embedding a gate electrode and overlying a substrate, a stack of a gate dielectric including a gate dielectric material, a dielectric diffusion barrier liner including a dielectric diffusion barrier material, and an active layer overlying a top surface of the gate electrode, and
a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. The dielectric diffusion barrier material is different from the gate dielectric material and is selected from a dielectric metal oxide material and a dielectric compound of silicon, and suppresses loss of metallic elements during subsequent anneal processes.-
4.发明公开公开(公告)号：US20240023341A1
公开(公告)日：2024-01-18
申请号：US18354858
申请日：2023-07-19
CPC分类号： H10B51/30 , H01L29/516 , H01L29/6684 , H01L29/78391 , H01L29/40111
摘要： A ferroelectric tunnel junction (FTJ) memory device includes a bottom electrode located over a substrate, a top electrode overlying the bottom electrode, and a ferroelectric tunnel junction memory element located between the bottom electrode and the top electrode. The ferroelectric tunnel junction memory element includes at least one ferroelectric material layer and at least one tunneling dielectric layer.
-
公开(公告)号：US11183504B2
公开(公告)日：2021-11-23
申请号：US16852662
申请日：2020-04-20
发明人： Chenchen Jacob Wang , Yu-Ming Lin , Chi On Chui , Sai-Hooi Yeong , Bo-Feng Young
IPC分类号： H01L27/11507 , H01L27/07 , H01L27/06 , H01L23/522 , H01L49/02 , H01L21/56
摘要： A ferroelectric device structure includes an array of ferroelectric capacitors overlying a substrate, first metal interconnect structures electrically connecting each of first electrodes of the array of ferroelectric capacitors to a first metal pad embedded in a dielectric material layer, and second metal interconnect structures electrically connecting each of the second electrodes of the array of ferroelectric capacitors to a second metal pad embedded in the dielectric material layer. The second metal pad may be vertically spaced from the substrate by a same vertical separation distance as the first metal pad is from the substrate. First metal lines laterally extending along a first horizontal direction may electrically connect the first electrodes to the first metal pad, and second metal lines laterally extending along the first horizontal direction may electrically connect each of the second electrodes to the second metal pad.
-
公开(公告)号：US09484244B2
公开(公告)日：2016-11-01
申请号：US14250911
申请日：2014-04-11
发明人： Sheng-Chen Wang , Sai-Hooi Yeong , Tsung-Yao Wen , Yen-Ming Chen
IPC分类号： H01L21/8242 , H01L21/762 , H01L29/78 , H01L29/66
CPC分类号： H01L21/02274 , H01L21/0214 , H01L21/02167 , H01L21/0217 , H01L21/0228 , H01L21/283 , H01L21/3065 , H01L21/31111 , H01L21/76224 , H01L29/0649 , H01L29/0657 , H01L29/66795 , H01L29/66818 , H01L29/785
摘要： Structures and methods are provided for forming fin structures. A first fin structure is formed on a substrate. A shallow-trench-isolation structure is formed surrounding the first fin structure. At least part of the first fin structure is removed to form a cavity. A first material is formed on one or more side walls of the cavity. A second material is formed to fill the cavity, the second material being different from the first material. At least part of the STI structure is removed to form a second fin structure including the first material and the second material. At least part of the first material that surrounds the second material is removed to fabricate semiconductor devices.
摘要翻译： 提供了用于形成翅片结构的结构和方法。 在基板上形成第一翅片结构。 围绕第一翅片结构形成浅沟槽隔离结构。 第一鳍片结构的至少一部分被去除以形成空腔。 第一材料形成在空腔的一个或多个侧壁上。 形成第二材料以填充空腔，第二材料与第一材料不同。 STI结构的至少一部分被去除以形成包括第一材料和第二材料的第二鳍结构。 围绕第二材料的第一材料的至少一部分被去除以制造半导体器件。
-
公开(公告)号：US20240331740A1
公开(公告)日：2024-10-03
申请号：US18602521
申请日：2024-03-12
发明人： Chia-Ta Yu , Chia-En Huang , Sai-Hooi Yeong , Yih Wang , Yi-Ching Liu
摘要： One aspect of this description relates to a memory array. In some embodiments, the memory array includes a first memory cell coupled between a first local select line and a first local bit line, a second memory cell coupled between a second local select line and a second local bit line, a first switch coupled to a global bit line, a second switch coupled between the first local bit line and the first switch, and a third switch coupled between the second local select line and the first switch.
-
公开(公告)号：US12078607B2
公开(公告)日：2024-09-03
申请号：US17569680
申请日：2022-01-06
发明人： Chih-Yu Chang , Ken-Ichi Goto , Yen-Chieh Huang , Min-Kun Dai , Han-Ting Tsai , Sai-Hooi Yeong , Yu-Ming Lin , Chung-Te Lin
CPC分类号： G01N27/221 , G01R31/24 , G01R31/2648 , H01L22/14 , H01L27/14
摘要： A method of characterizing a wide-bandgap semiconductor material is provided. A substrate is provided, which includes a layer stack of a conductive material layer, a dielectric material layer, and a wide-bandgap semiconductor material layer. A mercury probe is disposed on a top surface of the wide-bandgap semiconductor material layer. Alternating-current (AC) capacitance of the layer stack is determined as a function of a variable direct-current (DC) bias voltage across the conductive material layer and the wide-bandgap semiconductor material layer. A material property of the wide-bandgap semiconductor material layer is extracted from a profile of the AC capacitance as a function of the DC bias voltage.
-
公开(公告)号：US11923459B2
公开(公告)日：2024-03-05
申请号：US17228534
申请日：2021-04-12
发明人： Hung Wei Li , Mauricio Manfrini , Sai-Hooi Yeong , Yu-Ming Lin
IPC分类号： H01L29/786 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/66 , H10B51/30 , H10B51/40 , H10B61/00 , H10B63/00
CPC分类号： H01L29/78618 , H01L29/401 , H01L29/41733 , H01L29/41775 , H01L29/42384 , H01L29/66742 , H01L29/78642 , H01L29/7869 , H01L29/78696 , H10B51/30 , H10B51/40 , H10B61/22 , H10B63/34 , H10B63/80
摘要： A thin film transistor and method of making the same, the thin film transistor including: a substrate; a word line disposed on the substrate; a semiconductor layer disposed on the substrate, the semiconductor layer having a source region, a drain region, and a channel region disposed between the source and drain regions and overlapping with the word line in a vertical direction perpendicular to a plane of the substrate; a hydrogen diffusion barrier layer overlapping with the channel region in the vertical direction; a gate dielectric layer disposed between the channel region and the word line; and source and drain electrodes respectively electrically coupled to the source and drain regions.
-
公开(公告)号：US11805657B2
公开(公告)日：2023-10-31
申请号：US17229926
申请日：2021-04-14
CPC分类号： H10B51/30 , H01L29/40111 , H01L29/516 , H01L29/6684 , H01L29/78391
摘要： A ferroelectric tunnel junction (FTJ) memory device includes a bottom electrode located over a substrate, a top electrode overlying the bottom electrode, and a ferroelectric tunnel junction memory element located between the bottom electrode and the top electrode. The ferroelectric tunnel junction memory element includes at least one ferroelectric material layer and at least one tunneling dielectric layer.
-
-
-
-
-
-
-
-
-
搜索结果
32 条记录 (耗时 0.029 秒)
