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124 条记录 (耗时 0.054 秒)

    Method for forming MOS devices with retrograde pocket regions and counter dopant regions buried in the substrate surface
    21.
    发明授权
    Method for forming MOS devices with retrograde pocket regions and counter dopant regions buried in the substrate surface 失效
    用于形成埋置在衬底表面中的逆行袋区和反掺杂区的MOS器件的方法

    公开(公告)号：US5985727A

    公开(公告)日：1999-11-16

    申请号：US885071

    申请日：1997-06-30

    申请人： James B. Burr

    发明人： James B. Burr

    IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78

    CPC分类号： H01L29/66659 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/7835

    摘要： Disclosed is a low threshold asymmetric MOS device having a pocket region with a graded concentration profile. The pocket region includes a relatively high dopant atom concentration (of the same conductivity type as the bulk region) abutting either the device's source or its drain along the side of the source or drain that faces the device's channel region. The pocket region's graded concentration profile provides a lower dopant concentration near the substrate surface and an increasing dopant concentration below that surface. This provides a relatively low resistance conduction path through the pocket region, while allowing the device's threshold voltage to be somewhat higher at the pocket region. The asymmetric device can also include a counter dopant region located beneath its substrate surface. This forces current to flow in the substrate but just above the region of high counter dopant concentration, where the resistance is relatively low.

    摘要翻译： 公开了具有分级浓度分布的口袋区域的低阈值非对称MOS器件。 袋区域包括与器件的沟道区域相对的源或漏侧的器件的源极或漏极的相对高的掺杂剂原子浓度（与体区相同的导电类型）。 口袋区域的渐变浓度分布在基底表面附近提供较低的掺杂剂浓度，并且在该表面下方增加的掺杂剂浓度。 这提供了通过袋区域的相对较低的电阻传导路径，同时允许器件的阈值电压在口袋区域稍高一些。 不对称装置还可以包括位于其衬底表面下方的反掺杂剂区域。 这迫使电流在衬底中流动，但刚好高于高对位掺杂剂浓度的区域，其中电阻相对较低。

    Asymmetric low power MOS devices
    22.
    发明授权
    Asymmetric low power MOS devices 失效
    不对称低功耗MOS器件

    公开(公告)号：US5780912A

    公开(公告)日：1998-07-14

    申请号：US675804

    申请日：1996-07-05

    申请人： James B. Burr ,  Michael P. Brassington

    发明人： James B. Burr ,  Michael P. Brassington

    IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/788 ,  H01L29/94

    CPC分类号： H01L29/66659 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/7832 ,  H01L29/7833

    摘要： Low threshold voltage MOS devices having asymmetric halo implants are disclosed herein. An asymmetric halo implant provides a pocket region located under a device's source or drain near where the source (or drain) edge abuts the device's channel region. The pocket region has the same conductivity type as the device's bulk (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain. Only the source or drain, not both, have the primary pocket region. An symmetric halo device behaves like two pseudo-MOS devices in series: a "source FET" and a "drain FET." If the pocket implant is located under the source, the source FET will have a higher threshold voltage and a much shorter effective channel length than the drain FET.

    摘要翻译： 本文公开了具有不对称晕轮植入物的低阈值电压MOS器件。 非对称晕轮植入物提供位于器件源极或漏极附近的位于源极（或漏极）边缘靠近器件的沟道区域的口袋区域。 口袋区域具有与器件体积相同的导电类型（尽管具有较高的掺杂剂浓度），当然还有与器件的源极和漏极相反的导电类型。 只有源或漏极，而不是两者都具有初级口袋区域。 一个对称的晕圈器件类似于两个串联的伪MOS器件：“源FET”和“漏极FET”。 如果袋式注入位于源极之下，则源FET将具有比漏极FET更高的阈值电压和更短的有效沟道长度。

    Dynamic clocked inverter latch with reduced charge leakage
    23.
    发明授权
    Dynamic clocked inverter latch with reduced charge leakage 失效
    动态时钟反相器锁存器，减少电荷泄漏

    公开(公告)号：US5606270A

    公开(公告)日：1997-02-25

    申请号：US357607

    申请日：1994-12-16

    申请人： Godfrey P. D'Souza ,  James F. Testa ,  Douglas A. Laird ,  James B. Burr

    发明人： Godfrey P. D'Souza ,  James F. Testa ,  Douglas A. Laird ,  James B. Burr

    IPC分类号： H03K3/356 ,  H03K19/00 ,  H03K19/096 ,  H03K19/20

    CPC分类号： H03K19/0963 ,  H03K19/0016

    摘要： A dynamic clocked inverter latch with reduced charge leakage includes a first node biasing circuit with a P-MOSFET and an N-MOSFET totem-pole-coupled between VDD and an output node, and a second node biasing circuit with another N-MOSFET and another P-MOSFET totem-pole-coupled between the output node and VSS. The first P-MOSFET receives an input data signal and the first N-MOSFET receives a clock signal and in accordance therewith together cause the output node to charge to a charged state having a charge voltage associated therewith. The second N-MOSFET also receives the input data signal while the second P-MOSFET receives the inverse of the clock signal and in accordance therewith together cause the output node to discharge to a discharged state having a discharge voltage associated therewith. During inactive states of the clock signal, the first N-MOSFET becomes reverse-biased by the output node discharge voltage, while during inactive states of the inverse clock signal, the second P-MOSFET becomes reverse-biased by the output node charge voltage, thereby virtually eliminating charge leakage to and from the output node, respectively.

    摘要翻译： 具有减小的电荷泄漏的动态时钟反相器锁存器包括具有P-MOSFET的第一节点偏置电路和VDD与输出节点之间的N-MOSFET图腾柱耦合，以及具有另一N-MOSFET和另一N-MOSFET的第二节点偏置电路 输出节点和VSS之间的P-MOSFET图腾柱耦合。 第一P-MOSFET接收输入数据信号，并且第一N-MOSFET接收时钟信号，并且根据它们一起导致输出节点充电到具有与其相关联的充电电压的充电状态。 第二N-MOSFET还接收输入数据信号，而第二P-MOSFET接收到时钟信号的反相，并且根据它们一起使得输出节点放电到具有与其相关联的放电电压的放电状态。 在时钟信号的非活动状态期间，第一N-MOSFET由输出节点放电电压反向偏置，而在反时钟信号的非活动状态期间，第二P-MOSFET由输出节点充电电压反向偏置， 从而实际上分别消除了来自输出节点的电荷泄漏。

    Systems and methods for integrated circuits comprising multiple body biasing domains
    26.
    发明授权
    Systems and methods for integrated circuits comprising multiple body biasing domains 有权
    包括多个主体偏置域的集成电路的系统和方法

    公开(公告)号：US08697512B2

    公开(公告)日：2014-04-15

    申请号：US12968032

    申请日：2010-12-14

    申请人： Kleanthes G. Koniaris ,  Robert Paul Masleid ,  James B. Burr

    发明人： Kleanthes G. Koniaris ,  Robert Paul Masleid ,  James B. Burr

    IPC分类号： H01L29/72

    CPC分类号： H03K19/0027 ,  H03K2217/0018

    摘要： Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of second type material extends from a surface of the substrate to a first depth. A planar deep well of said second type material underlying and coupled to the closed structure extends from the first depth to a second depth. The closed structure and the planar deep well of said second type material form an electrically isolated region of the first type material. A second-type semiconductor device is disposed to receive a first body biasing voltage from the electrically isolated region of the first type material. A well of the second-type material within the electrically isolated region of the first type material is formed and a first-type semiconductor device is disposed to receive a second body biasing voltage from the well of second-type material.

    摘要翻译： 包括多个主体偏置域的集成电路的系统和方法。 根据第一实施例，半导体结构包括第一类型材料的衬底。 包括第二类型材料的壁的第一封闭结构从衬底的表面延伸到第一深度。 所述第二类型材料的下面并耦合到所述封闭结构的平面深井从所述第一深度延伸到第二深度。 所述第二类型材料的封闭结构和平面深孔形成第一类型材料的电隔离区域。 第二类型半导体器件设置成从第一类型材料的电隔离区域接收第一主体偏置电压。 形成在第一类型材料的电隔离区域内的第二类型材料的阱，并且设置第一类型半导体器件以从第二类型材料的阱接收第二主体偏置电压。

    SYSTEMS AND METHODS FOR ADJUSTING THRESHOLD VOLTAGE
    28.
    发明申请
    SYSTEMS AND METHODS FOR ADJUSTING THRESHOLD VOLTAGE 有权
    调整阈值电压的系统和方法

    公开(公告)号：US20120281483A1

    公开(公告)日：2012-11-08

    申请号：US13550459

    申请日：2012-07-16

    申请人： Robert Paul Masleid ,  James B. Burr

    发明人： Robert Paul Masleid ,  James B. Burr

    IPC分类号： G11C7/22 ,  G11C27/00 ,  G11C17/16 ,  G11C16/10

    CPC分类号： H03K19/0027 ,  G01R31/2621 ,  H03K2217/0018

    摘要： Systems and methods for adjusting threshold voltage. A threshold voltage of a transistor of an integrated circuit is measured. A bias voltage, which when applied to a body well of the transistor corrects a difference between the threshold voltage and a desired threshold voltage for the transistor, is determined. The bias voltage is encoded into non-volatile storage on the integrated circuit. The non-volatile storage can be digital and/or analog.

    摘要翻译： 用于调整阈值电压的系统和方法。 测量集成电路的晶体管的阈值电压。 当施加到晶体管的体阱时，偏置电压校正阈值电压和晶体管的期望阈值电压之间的差异。 偏置电压被编码到集成电路上的非易失性存储器中。 非易失性存储器可以是数字和/或模拟的。

    Method for generating a deep N-well pattern for an integrated circuit design
    29.
    发明授权
    Method for generating a deep N-well pattern for an integrated circuit design 失效
    用于生成用于集成电路设计的深N阱图案的方法

    公开(公告)号：US08146037B2

    公开(公告)日：2012-03-27

    申请号：US12544149

    申请日：2009-08-19

    申请人： Michael Pelham ,  James B. Burr

    发明人： Michael Pelham ,  James B. Burr

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： A method for the design and layout for a patterned deep N-well. A tile is specified as a fundamental building block for the deep N-well pattern. The tile comprises a first element on a first layer and may comprise a second element on a second layer. A two dimensional region is covered with an array of contiguous tiles, with the elements on each layer connecting with elements of adjacent tiles to form extended shapes. The array may be converted to a collection of sub-arrays through the removal of tiles. The array or collection of sub-arrays may be merged to produce a first layer pattern and second layer pattern. Design rule checks may be applied to verify the pattern. The first layer shapes and second layer shapes may be edited. The first layer shapes and the second layer shapes may then be combined to produce a deep N-well pattern.

    摘要翻译： 一种用于图案化深N阱的设计和布局的方法。 将瓷砖指定为深N型图案的基本构建块。 瓦片包括在第一层上的第一元件，并且可以包括在第二层上的第二元件。 二维区域覆盖有连续瓦片阵列，每层上的元素与相邻瓦片的元素连接以形成延伸形状。 阵列可以通过去除瓦片而转换为子阵列的集合。 子阵列的阵列或集合可以被合并以产生第一层图案和第二层图案。 可以应用设计规则检查来验证模式。 可以编辑第一层形状和第二层形状。 然后可以组合第一层形状和第二层形状以产生深N阱图案。

    Systems and methods for integrated circuits comprising multiple body biasing domains
    30.
    发明授权
    Systems and methods for integrated circuits comprising multiple body biasing domains 有权

    公开(公告)号：US07816742B1

    公开(公告)日：2010-10-19

    申请号：US11400368

    申请日：2006-04-06

    申请人： Kleanthes G. Koniaris ,  Robert Paul Masleid ,  James B. Burr

    发明人： Kleanthes G. Koniaris ,  Robert Paul Masleid ,  James B. Burr

    IPC分类号： H01L29/72

    CPC分类号： H01L21/823892 ,  H01L21/743 ,  H01L21/761 ,  H01L21/823878 ,  H01L29/78

    摘要： Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment of the present invention, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of second type material extends from a surface of the substrate to a first depth. A planar deep well of said second type material underlying and coupled to the closed structure extends from the first depth to a second depth. The closed structure and the planar deep well of said second type material form an electrically isolated region of the first type material. A second-type semiconductor device is disposed to receive a first body biasing voltage from the electrically isolated region of the first type material. A well of the second-type material within the electrically isolated region of the first type material is formed and a first-type semiconductor device is disposed to receive a second body biasing voltage from the well of second-type material.